ISL6334ACRZ-T Datasheet, PDF (20/31 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features

ISL6334, ISL6334A
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
C_REF
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
OFS
ISL6334, ISL6334A
VCC
GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their core
voltage as part of normal operation. They direct the core-
voltage regulator to do this by making changes to the VID
inputs during regulator operation. The power management
solution is required to monitor the DAC inputs and respond to
on-the-fly VID changes in a controlled manner. Supervising
the safe output voltage transition within the DAC range of the
processor without discontinuity or disruption is a necessary
function of the core-voltage regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, as shown in Figure 7, can be
used. The selection of R_REF is based on the desired offset
voltage as detailed in “Output-Voltage Offset Programming”
on page 19. The selection of C_REF is based on the time
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t_VID, the relationship between the time constant
of R_REF and C_REF network and t_VID is given by Equation 13.
C_REF R_REF = t_VID
(EQ. 13)
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334,
ISL6334A is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334, ISL6334A are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334, ISL6334A will not inadvertently turn off
unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
2. The ISL6334, ISL6334A features an enable input
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334, ISL6334A in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334, ISL6334A becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334, ISL6334A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions previously mentioned are satisfied,
ISL6334, ISL6334A begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334, ISL6334A reads the VID code at VID input
pins. If the VID code is valid, ISL6334, ISL6334A will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334, ISL6334A will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6334, ISL6334A based VR has 4 periods during soft-start,
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period t_D1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V V_BOOT
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t_D3. At the end of t_D3 period, ISL6334,
ISL6334A reads the VID signals. If the VID code is valid,
ISL6334, ISL6334A will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus offset voltage.
20
FN6482.2
February 1, 2013