ISL6314_14 Datasheet, PDF (21/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
t_d2 = 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 16)
t_d4 = V_VID – 1.1 ⋅ R_SS ⋅ 8 ⋅ 10^–3(μs)
(EQ. 17)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_d2 will be 880µs and the
second soft-start ramp time t_d4 will be 320µs.
After the DAC voltage reaches the final VID setting, PGOOD
will be set to high with the fixed delay t_d5. The typical value
for t_d5 is 93µs.
AMD Soft-Start
V_OUT, 500mV/DIV
TABLE 5. ISL6314 SOFT_START TIMING SUMMARY
MODE
TIME SLOT
TIME
VR11
VR11
VR11
VR11
VR11
AMD
AMD
t_d1
1.1ms
t_d2
Equation 16
t_d3
93µs
t_d4
Equation 17
t_d5
93µs
t_dA
1.1ms
t_dB
Equation 18
Pre-Biased Soft-Start
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
t_dA
t_dB
EN
PGOOD
500µs/DIV
FIGURE 12. AMD SOFT-START WAVEFORMS
For the AMD 5-bit and 6-bit modes of operation, the
soft-start sequence is composed of two periods, as shown in
Figure 12. At the beginning of soft-start, the VID code is
immediately obtained from the VID pins, followed by a fixed
delay period t_dA of typically 1.1ms. After this delay period the
ISL6314 will begin ramping the output voltage to the desired
DAC level at a fixed rate of 6.25mV per step. The time for
each step is determined by the frequency of the soft-start
oscillator which is defined by the resistor R_SS on the SS pin.
The amount of time required to ramp the output voltage to
the final DAC voltage is referred to as t_dB, and can be
calculated as shown in Equation 18.
t_dB
=
V_V
I
D
⋅
R
S
S
⋅
8
⋅
10^–3
(
μ
s
)
(EQ. 18)
At the end of soft-start, PGOOD will immediately go high if
the VSEN voltage is within the undervoltage and overvoltage
limits.
Table 5 is a summary table of the typical soft-start timing for
both modes. The times listed are fixed delays; the variable
ones (defined by the equations) depend on the slope of the
ramp (1.25 mV/µs for a nominal 100kΩ R_SS resistor), and
the amount of voltage excursion.
GND>
V_OUT (0.5V/DIV)
GND>
EN (5V/DIV)
T1 T2
T3
FIGURE 13. SOFT-START WAVEFORMS FOR ISL6314-BASED
CONVERTER
The ISL6314 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the DAC setting. Should the
output be pre-charged to a level exceeding the DAC setting,
the output drives are enabled at the end of the soft-start
period, leading to an abrupt correction in the output voltage
down to the DAC-set level. See Figure 13.
Fault Monitoring and Protection
The ISL6314 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 14
outlines the interaction between the fault monitors and the
power-good signal.
21
FN6455.2
October 8, 2009