ISL6314_14 Datasheet, PDF (20/32 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated MOSFET Drivers for Intel VR11 and AMD Applications

ISL6314
.
ISL6314 INTERNAL CIRCUIT
EXTERNAL CIRCUIT
POR
CIRCUIT
VCC
PVCC _+12V
ENABLE
COMPARATOR
+
-
10.7kΩ
EN
1.40kΩ
0.85V
4. The VID code must not be 11111 in AMD 5-bit mode. This
code signals the controller that no load is present. The
controller will not allow soft-start to begin if this VID code
is present on the VID pins.
Once all of these conditions are met the controller will begin
the soft-start sequence and will ramp the output voltage up
to the user designated level.
Intel Soft-Start
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. The soft-start sequence for the Intel modes of
operation is slightly different than the AMD soft-start
sequence.
SOFT-START
AND
FAULT LOGIC
FIGURE 10. POWER SEQUENCING USING
THRESHOLD-SENSITIVE ENABLE (EN)
FUNCTION
Enable and Disable
While in shutdown mode, the LGATE and UGATE signals
are held low to assure the MOSFETs remain off. The
following input conditions must be met, for both Intel and
AMD modes of operation, before the ISL6314 is released
from shutdown mode to begin the soft-start start-up
sequence:
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6314 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6314 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 6).
2. The voltage on EN must be above 0.85V. The EN input
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL6314 in shutdown until the voltage at EN
rises above 0.85V. The enable comparator has 110mV of
hysteresis to prevent bounce.
3. The driver bias voltage applied at the PVCC pin must
reach the internal power-on reset (POR) rising threshold.
Hysteresis between the rising and falling thresholds
assure that once enabled, the ISL6314 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 6).
For Intel VR11 and AMD 6-bit modes of operation these are
the only conditions that must be met for the controller to
immediately begin the soft-start sequence, as shown in
Figure 10. If running in AMD 5-bit mode of operation there is
one more condition that must be met:
V_OUT, 500mV/DIV
t_d1
t_d2
t_d3 t_d4 t_d5
EN
PGOOD
500µs/DIV
FIGURE 11. INTEL SOFT-START WAVEFORMS
For the Intel VR11 mode of operation, the soft-start
sequence is composed of four periods, as shown in
Figure 11. Once the ISL6314 is released from shutdown and
soft-start begins (as described in “Enable and Disable” on
page 20), the controller will have fixed delay period t_d1,
typically 1.1ms. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period t_d3, typically 93µs. At the end of
t_d3 period, ISL6314 will read the VID signals. It is
recommended that the VID codes be set no later then 50µs
into period t_d3. If the VID code is valid, ISL6314 will initiate
the second soft-start ramp until the output voltage reaches
the VID voltage plus/minus any offset or droop voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 15.
t_SS = t_d1 + t_d2 + t_d3 + t_d4
(EQ. 15)
During t_d2 and t_d4, ISL6314 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_SS from SS pin to GND. The
second soft-start ramp time t_d2 and t_d4 can be calculated
based on Equations 16 and 17:
20
FN6455.2
October 8, 2009