ISL6336B Datasheet, PDF (20/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring

ISL6336B
When all conditions above are satisfied, ISL6336B begins
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6336B reads the VID
code at VID input pins. If the VID code is valid, ISL6336B will
regulate the output to the final VID setting. If the VID code is
an OFF code, ISL6336B will shut down, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6336B based VR has 4 periods during soft-start as
shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, The controller will have fixed
delay period t_D1. After this delay period, the VR will begin
first soft-start ramp until the output voltage reaches 1.1V
V_BOOT voltage. Then, the controller will regulate the VR
voltage at 1.1V for another fixed period t_D3. At the end of t_D3
period, ISL6336B reads the VID signals. If the VID code is
valid, ISL6336B will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus the offset voltage.
VOUT, 500mV/DIV
t_D1
t_D2 t_D3 t_D4 t_D5
EN_VTT
VR_RDY
500µs/DIV
FIGURE 9. SOFT-START WAVEFORMS
The soft-start time is the sum of the 4 periods as shown in
Equation 14:
t_SS = t_D1 + t_D2 + t_D3 + t_D4
(EQ. 14)
t_D1 is a fixed delay with a typical value as 1.36ms. t_D3 is
determined by a fixed 85µs plus the time to obtain valid VID
voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t_D3 is about 86µs.
During t_D2 and t_D4, ISL6336B digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator, which
is defined by a resistor R_SS from SS pin to GND or VCC. The
equations are the same for the case where R_SS is connected
to GND or VCC. The two soft-start ramp times t_D2 and t_D4 can
be calculated based on the Equations 15 and 16:
t_D2
=
-1---.--1----^â‹---R-----^S----^S--
6.25 ⋅ 25
(
μ
s
)
(EQ. 15)
t_D4
=
(_---(_{--V-----V----I-D------}–_{----1----.-1----})_---⋅_{---R-----S----S----})
6.25 ⋅ 25
(
μ
s
)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_D2 will be 704µs and the
second soft-start ramp time t_D4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t_D5. The
typical value for t_D5 is 85µs. Before VR_RDY is released,
the controller disregards the PSI# input and always operates
in normal CCM PWM mode.
Current Sense Output
The current sourced at the IMON pin is equal to the sensed
average current inside the ISL6336B, I_AVG. In a typical
application, a resistor is placed from the IMON pin to GND to
generate a voltage which is proportional to the load current
as shown in Equation 17:
V_IMON
=
-R----^I--^M-----^O----^N--
N
⋅
------^R----^X-------
R_ISEN
⋅
I_O
U
T
(EQ. 17)
where V_IMON is the voltage at the IMON pin, R_IMON is the
resistor between IMON and GND, I_OUT is the total output
current of the converter, R_ISEN is the sense resistor
connected to the ISEN+ pin, N is the active channel number
and R_X is the DC resistance of the current sense element.
The resistor from the IMON pin to GND should be chosen to
ensure that the voltage at the IMON pin is less than 1.12V
under the maximum load current. The IMON pin voltage is
clamped at a maximum of 1.12V. Once the 1.12V threshold
is reached, an overcurrent shutdown will be initiated as
described in “Overcurrent Protection” on page 21.
A small capacitor can be placed between the IMON pin and
GND to reduce noise. In addition, some applications will
require the V_IMON signal to be filtered with a minimum time
constant. The filter capacitor can be chosen appropriately
based on the R_IMON value to set the desired time constant.
V_{IMON_OFS}
0V
0A ^{LOAD INCREASING}
FIGURE 10. IMON VOLTAGE vs OUTPUT CURRENT
The voltage at the IMON pin will vary linearly with output
current, as shown in Figure 10 with some tolerance. Some
applications may require the addition of a positive offset on
20
FN6696.2
August 31, 2010