ISL6336B Datasheet, PDF (19/31 Pages) Intersil Corporation – 6-Phase PWM Controller with Light Load Efficiency Enhancement and Current Monitoring

ISL6336B
FB
-
E/A
+
DYNAMIC
VID D/A
DAC
R_REF
REF
C_REF
+
-
-
-
1.6V
+
+
+
0.4V
-
VCC
OR
GND
R_OFS
OFS
ISL6336B
VCC
GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of the normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during the regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure a smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, can be used. The selection of
R_REF is based on the desired offset voltage as detailed
above in “Output-Voltage Offset Programming” on page 18.
The selection of C_REF is based on the time duration for 1-bit
VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t_VID, the relationship between the time constant
of R_REF and C_REF network and t_VID is given by Equation 13.
C_REF ⋅ R_REF = t_VID
(EQ. 13)
During dynamic VID transition and VID up steps, the
overcurrent trip point increases by 140% to avoid false
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If dynamic VID occurs
when PSI# is asserted, the controller will activate all phases
and complete the transition at which point the status of the
PSI# pin will control operation.
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, VR_RDY asserts logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6336B
is released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6336B is guaranteed. Hysteresis between the
rising and falling thresholds assure that once enabled,
the ISL6336B will not inadvertently turn off unless the
bias voltage drops substantially (see “Electrical
Specifications” table beginning on page 7).
2. The ISL6336B features an enable input (EN_PWR) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6336B in shutdown until the voltage at EN_PWR rises
above 0.875V. The enable comparator has about 130mV
of hysteresis to prevent bounce. It is important that the
driver ICs reach their POR level before the ISL6336B
becomes enabled. The schematic in Figure 8
demonstrates sequencing the ISL6336B with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of the VTT voltage regulator.
ISL6336B INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
100kΩ
EN_PWR
9.1kΩ
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 8. POWER SEQUENCING USING THRESHOLD
SENSITIVE ENABLE (EN) FUNCTION
19
FN6696.2
August 31, 2010