ISL6334 Datasheet, PDF (20/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring

ISL6334, ISL6334A
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6334, ISL6334A are guaranteed. Hysteresis
between the rising and falling thresholds assure that once
enabled, ISL6334, ISL6334A will not inadvertently turn off
unless the bias voltage drops substantially (see
“Electrical Specifications” table beginning on page 8).
2. The ISL6334, ISL6334A features an enable input
(EN_PWR) for power sequencing between the controller
bias voltage and another voltage rail. The enable
comparator holds the ISL6334, ISL6334A in shutdown
until the voltage at EN_PWR rises above 0.875V. The
enable comparator has about 130mV of hysteresis to
prevent bounce. It is important that the driver reach their
POR level before the ISL6334, ISL6334A becomes
enabled. The schematic in Figure 8 demonstrates
sequencing the ISL6334, ISL6334A with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions previously mentioned are satisfied,
ISL6334, ISL6334A begins the soft-start and ramps the
output voltage to 1.1V first. After remaining at 1.1V for some
time, ISL6334, ISL6334A reads the VID code at VID input
pins. If the VID code is valid, ISL6334, ISL6334A will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6334, ISL6334A will shut down, and cycling
VCC, EN_PWR or EN_VTT is needed to restart.
ISL6334, ISL6334A INTERNAL CIRCUIT
EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
100kΩ
EN_PWR
9.1kΩ
+
EN_VTT
-
Soft-Start
ISL6334, ISL6334A based VR has 4 periods during soft-start,
as shown in Figure 9. After VCC, EN_VTT and EN_PWR reach
their POR/enable thresholds, the controller will have a fixed
delay period t_D1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V Vboot
voltage. Then, the controller will regulate the VR voltage at 1.1V
for another fixed period t_D3. At the end of t_D3 period, ISL6334,
ISL6334A reads the VID signals. If the VID code is valid,
ISL6334, ISL6334A will initiate the second soft-start ramp until
the voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 14.
t_SS = t_D1 + t_D2 + t_D3 + t_D4
(EQ. 14)
t_D1 is a fixed delay with the typical value as 1.36ms. t_D3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore, the minimum t_D3 is about 86µs.
During t_D2 and t_D4, ISL6334, ISL6334A digitally controls the
DAC voltage change at 6.25mV per step. The time for each
step is determined by the frequency of the soft-start
oscillator, which is defined by the resistor R_SS from SS pin to
GND. The second soft-start ramp time t_D2 and t_D4 can be
calculated based on Equations 15 and 16:
t_D2
=
1----.--1---x----R----_S----S--
6.25 x 25
(
μ
s
)
(EQ. 15)
t_D4
=
(_{---V----V----I--D-----}–_{-----1---.--1----})_{--x---R-----S----S--}
6.25 x 25
(
μ
s
)
(EQ. 16)
For example, when VID is set to 1.5V and the R_SS is set at
100kΩ, the first soft-start ramp time t_D2 will be 704µs and the
second soft-start ramp time t_D4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t_D5. The
typical value for t_D5 is 85µs. Before the VR_RDY is
released, the controller disregards the PSI# input and
always operates in normal CCM PWM mode.
VOUT, 500mV/DIV
SOFT-START
AND
FAULT LOGIC
0.875V
t_D1
t_D2 t_D3 t_D4 t_D5
EN_VTT
FIGURE 8. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
VR_RDY
500µs/DIV
FIGURE 9. SOFT-START WAVEFORMS
20
FN6482.0
February 26, 2008