ISL6334 Datasheet, PDF (19/30 Pages) Intersil Corporation – VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring

ISL6334, ISL6334A
The regulated output voltage is reduced by the droop voltage
V_DROOP. The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed, as shown in Equation 9:
V_OUT
=
V_REF
–
V_O
F
S
–
⎛
⎜
⎝
I--_{L----O----A----D--}
N
------R----^X-------
R_ISEN
⎞
R _{F B⎠⎟}
(EQ. 9)
where V_REF is the reference voltage, V_OFS is the
programmed offset voltage, I_LOAD is the total output current
of the converter, R_ISEN is the sense resistor connected to
the ISEN+ pin, and R_FB is the feedback resistor, N is the
active channel number, and R_X is the DCR, or R_SENSE
depending on the sensing method.
Therefore, the equivalent loadline impedance, i.e. Droop
impedance, is equal to Equation 10:
R_LL
=
--R----^F----^B--
N
-----R-----^X-------
R_ISEN
(EQ. 10)
Output-Voltage Offset Programming
The ISL6334, ISL6334A allows the designer to accurately
adjust the offset voltage. When a resistor, R_OFS, is
connected between OFS to VCC, the voltage across it is
regulated to 1.6V. This causes a proportional current (I_OFS)
to flow into OFS. If R_OFS is connected to ground, the voltage
across it is regulated to 0.4V, and I_OFS flows out of OFS. A
resistor between DAC and REF, R_REF, is selected so that
the product (I_OFS x R_OFS) is equal to the desired offset
voltage. These functions are shown in Figure 7.
FB
DYNAMIC
VID D/A
DAC
R_REF
E/A
REF
C_REF
VCC
OR
GND
-
1.6V
+
+
0.4V
-
R_OFS
OFS
ISL6334, ISL6334A
VCC
GND
FIGURE 7. OUTPUT VOLTAGE OFFSET PROGRAMMING
Once the desired output offset voltage has been determined,
use Equations 11 and 12 to calculate R_OFS:
For Positive Offset (connect R_OFS to VCC):
R_OFS
=
1_----._--6_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 11)
For Negative Offset (connect R_OFS to GND):
R_OFS
=
0_----._--4_----×_-----R_{-----R----E----F-}
V_OFFSET
(EQ. 12)
Dynamic VID
Modern microprocessors need to make changes to their
core voltage as part of normal operation. They direct the
core-voltage regulator to do this by making changes to the
VID inputs during regulator operation. The power
management solution is required to monitor the DAC inputs
and respond to on-the-fly VID changes in a controlled
manner. Supervising the safe output voltage transition within
the DAC range of the processor without discontinuity or
disruption is a necessary function of the core-voltage
regulator.
In order to ensure the smooth transition of output voltage
during VID change, a VID step change smoothing network,
composed of R_REF and C_REF, as shown in Figure 7, can be
used. The selection of R_REF is based on the desired offset
voltage as detailed in “Output-Voltage Offset Programming”
on page 19. The selection of C_REF is based on the time
duration for 1-bit VID change and the allowable delay time.
Assuming the microprocessor controls the VID change at
1-bit every t_VID, the relationship between the time constant
of R_REF and C_REF network and t_VID is given by Equation 13.
C_REF R_REF = t_VID
(EQ. 13)
During dynamic VID transition and VID steps up, the
overcurrent trip point increases by 140% to avoid falsely
triggering OCP circuits, while the overvoltage trip point is set
to its maximum VID OVP trip level. If the dynamic VID occurs
at PSI# asserted, the system should exit PSI# and complete
the transition, and then resume PSI# operation 50µs after
the transition.
Operation Initialization
Prior to converter initialization, proper conditions must exist
on the enable inputs and VCC. When the conditions are met,
the controller begins soft-start. Once the output voltage is
within the proper window of operation, VR_RDY asserts
logic high.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6334,
ISL6334A is released from shutdown mode.
19
FN6482.0
February 26, 2008