ISL6244 Datasheet, PDF (20/25 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6244
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the L-C
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 26, provides the necessary
compensation.
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than 1/3
of the switching frequency. The type-III compensator has an
extra high-frequency pole, f_HF. This pole can be used for added
noise rejection or to assure adequate attenuation at the error-
amplifier high-order pole and zero frequencies. A good general
rule is to chose f_HF = 10f₀, but it can be higher if desired.
Choosing f_HF to be lower than 10f₀ can cause problems with
too much phase shift below the system bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equations 25, R_FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equations 25.
R₁
=
R_FB
----------C----⁽---E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L----C-----^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
-----------------------0---.--7----5---V-----^I-^N-------------------------
(2π)²f₀f_HF LCR_FBV_PP
R_C
=
---V-----^P----^P----^--2----^π---^---²----f--⁰---f--^H----^F----L----C----R-----^F----^B----
0.75 V_{IN }2πf_HF LC–1_
C_C
=
--0----.-7----5----V----^I--^N----^-2----^π----f--^H----^F--------L----C-----^–---1---^---
(2π)²f₀f_HF LCR_FBV_PP
(EQ. 25)
In Equations 25, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 16 and Electrical Specifications.
Output Filter Design
The output inductors and the output capacitor bank together
form a low-pass filter responsible for smoothing the pulsating
voltage at the phase nodes. The output filter also must
provide the transient energy during the interval of time after
the beginning of the transient until the regulator can
respond. Because it has a low bandwidth compared to the
switching frequency, the output filter necessarily limits the
system transient response leaving the output capacitor bank
to supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
In high-speed converters, the output capacitor bank is
usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
this part of the circuit. The critical load parameters in
choosing the output capacitors are the maximum size of the
load step, ∆I; the load-current slew rate, di/dt; and the
maximum allowable output-voltage deviation under transient
loading, ∆V_MAX. Capacitors are characterized according to
their capacitance, ESR, and ESL (equivalent series
inductance).
At the beginning of the load transient, the output capacitors
supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
drop across the ESL. As the load current increases, the
voltage drop across the ESR increases linearly until the
load current reaches its final value. The capacitors selected
must have sufficiently low ESL and ESR so that the total
output-voltage deviation is less than the allowable
maximum. Neglecting the contribution of inductor current
and regulator response, the output voltage initially deviates
by an amount
∆V ≈ (ESL) -d---i + (ESR) ∆I
dt
(EQ. 26)
The filter capacitor must have sufficiently low ESL and ESR
so that ∆V < ∆V_MAX.
Most capacitor solutions rely on a mixture of high-frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see Interleaving and
Equation 2), a voltage develops across the bulk-capacitor
ESR equal to I_C,PP (ESR). Thus, once the output capacitors
are selected, the maximum allowable ripple voltage,
V_PP(MAX), determines the lower limit on the inductance.
L
≥
(ESR)


V_IN
–
N
V_O
U

T_
V_OUT
-----------------------------------------------------------
f_S V_{I N} V_{P P( M A X )}
(EQ. 27)
20
FN9106.3
December 28, 2004