ISL6244 Datasheet, PDF (13/25 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6244
TABLE 1. VOLTAGE IDENTIFICATION CODES
VID4
VID3 VID2 VID1 VID0
DAC
0
0
0
0
0
1.550
0
0
0
0
1
1.525
0
0
0
1
0
1.500
0
0
0
1
1
1.475
0
0
1
0
0
1.450
0
0
1
0
1
1.425
0
0
1
1
0
1.400
0
0
1
1
1
1.375
0
1
0
0
0
1.350
0
1
0
0
1
1.325
0
1
0
1
0
1.300
0
1
0
1
1
1.275
0
1
1
0
0
1.250
0
1
1
0
1
1.225
0
1
1
1
0
1.200
0
1
1
1
1
1.175
1
0
0
0
0
1.150
1
0
0
0
1
1.125
1
0
0
1
0
1.100
1
0
0
1
1
1.075
1
0
1
0
0
1.050
1
0
1
0
1
1.025
1
0
1
1
0
1.000
1
0
1
1
1
0.975
1
1
0
0
0
0.950
1
1
0
0
1
0.925
1
1
0
1
0
0.900
1
1
0
1
1
0.875
1
1
1
0
0
0.850
1
1
1
0
1
0.825
1
1
1
1
0
0.800
1
1
1
1
1
Shutdown
The integrating compensation network shown in Figure 17
assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
sense and error amplifiers. Intersil specifies the guaranteed
tolerance of the ISL6244 to include all variations in current
sources, amplifiers and the reference so that the output
voltage remains within the specified system tolerance of
±1%. The 1% does not include the VID offset tolerance or
any external component tolerances.
FEED-FORWARD RAMP COMPENSATION
The ISL6244 features a V_FF pin for setting the pulse width
modulator gain. The V_FF voltage is set by a resistor divider
network from the battery voltage, as illustrated in Figure 18.
The V_FF voltage sets the peak-to-peak voltage of the ramp
oscillator relative to the battery voltage. By feeding the
battery voltage forward, the pulse width modulation gain,
G_mod, is independent of battery voltage, see Equation 5.
G_mod
=
----------------^d-----^M-----^A-----^X-----^â‹---^V----^B-----^A----^T----^T-----^E----^R-----^Y------------------
R^------_A^----_D^-----R_J^---₁^--A----+^-D----R^J----2-_A^-----_D^-----_J^---₂^{-- ⋅ VBATTERY}
=
0.75 x 10
=
7.5
(EQ. 5)
The ramp modulator gain is then set by the ratio of the
maximum duty cycle, d_MAX, to the amount of attenuation
programmed by the resistor network on the V_FF pin. For
typical applications, select R_ADJ1 to be 9 times the value of
R_ADJ2 for a 1/10 attenuation of the battery voltage, resulting
in a constant pulse width modulator gain of 7.5 over the
entire range of battery voltage (see note below).
NOTE: the V_FF voltage must be bounded between 0.5V and 2.5V.
.
V_COMP
PWM
+
SAWTOOTH
-
GENERATOR
SAWTOOTH
SIGNAL
V_BATTERY
PWM1
R_ADJ1
V_FF
R_ADJ2
ISL6244 INTERNAL CIRCUITRY
FIGURE 18. BATTERY VOLTAGE FEED-FORWARD
COMPENSATION
LOAD-LINE REGULATION
Microprocessor load current demands change from near no-
load to full load often during operation. The resulting sizable
transient current slew rate causes an output voltage spike
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the
spike is dictated by the ESR and ESL of the output
capacitors selected. In order to drive the cost of the output
capacitor solution down, one commonly accepted approach
is active voltage positioning. By adding a well controlled
output impedance, the output voltage can effectively be level
shifted in a direction which works against the voltage spike.
The average current of all the active channels, I_AVG, flows
out IOUT, see Figure 17. IOUT is connected to FB through a
load-line regulation resistor, R_FB. The resulting voltage drop
across R_FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined as
V_DROOP = I_AVG R_FB
(EQ. 6)
13
FN9106.3
December 28, 2004