ISL6244 Datasheet, PDF (12/25 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6244
V_COMP
+
-
f(jω)
+
-
SAWTOOTH SIGNAL
I_ER
I_{AVG ÷ N}
Σ
-
+
PWM1
I₄ *
I₃ *
I₂
I₁
NOTE: *Channels 3 and 4 are optional.
FIGURE 16. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
Two considerations designers face are MOSFET selection
and inductor design. Both are significantly improved when
channel currents track at any load level. The need for
complex drive schemes for multiple MOSFETs, exotic
magnetic materials, and expensive heat sinks is avoided,
resulting in a cost-effective and easy to implement solution
relative to single-phase conversion. Channel-current
balance insures the thermal advantage of multi-phase
conversion is realized. Heat dissipation is spread over
multiple channels and a greater area than single phase
approaches.
Voltage Regulation
The output of the error amplifier, V_COMP, is compared to the
sawtooth waveform to modulate the pulse width of the PWM
signals. The PWM signals control the timing of the Intersil
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
amplifier determine the voltage level of V_COMP. The internal
and external circuitry which control voltage regulation is
illustrated in Figure 17.
Most multi-phase controllers simply have the output voltage
fed back to the inverting input of the error amplifier through a
resistor. The ISL6244 features an internal differential
remote-sense amplifier in the feedback path. The amplifier
removes the voltage error encountered when measuring the
output voltage relative to the local controller ground
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense
pins to the non-inverting input, VSEN, and inverting input,
RGND, of the remote-sense amplifier. The remote-sense
amplifier output, V_DIFF, is then tied through an external
resistor to the inverting input of the error amplifier.
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4
through VID0. The DAC decodes a 5-bit logic signal (VID)
into one of the discrete voltages shown in Table 1. Each VID
input offers a 20µA pull-up to an internal 2.5V source for use
with open-drain outputs. External pull-up resistors or active-
high output stages can augment the pull-up current sources,
but a slight accuracy error can occur if they are pulled above
2.9V. The DAC-selected reference voltage is connected to
the non-inverting input of the error amplifier.
The ISL6244 features a second non-inverting input to the
error amplifier which allows the user to directly offset the
DAC reference voltage in the positive direction only. The
offset voltage is created by an internal current source which
feeds out the OFS pin into a user selected external resistor
to ground.
EXTERNAL CIRCUIT
R_C
C_C
COMP
FB
R_FB
+
V_DROOP
-
IOUT
VDIFF
ISL6244 INTERNAL CIRCUIT
ERROR AMPLIFIER
-
I_AVG
+
+
V_COMP
REFERENCE
VOLTAGE
V_OUT
REMOTE
SENSE
POINTS
GND
VSEN
RGND
R_OFS
OFS
+
V_OFS
-
+
-
DIFFERENTIAL
REMOTE-SENSE
AMPLIFIER
1/5
100µA
OFFSET
VOLTAGE
FIGURE 17. OUTPUT-VOLTAGE AND LOAD-LINE
REGULATION
The resulting voltage across the resistor, V_OFS, is internally
divided down by five to create the offset voltage. This
method of offsetting the DAC voltage is more accurate than
external methods of level-shifting the FB pin.
12
FN9106.3
December 28, 2004