ISL6244 Datasheet, PDF (19/25 Pages) Intersil Corporation – Multi-Phase PWM Controller

ISL6244
COMPENSATING LOAD-LINE REGULATED
CONVERTER
The load-line regulated converter behaves in a similar
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with
the introduction of current information into the control loop.
The final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R_C and C_C.
C₂ (OPTIONAL)
R_C ^CC
COMP
R_FB
+
V_DROOP
-
FB
IOUT
VDIFF
FIGURE 25. COMPENSATION CONFIGURATION FOR
LOAD-LINE REGULATED ISL6244 CIRCUIT
Since the system poles and zero are effected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator by compensating the L-C
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R_FB, has already been chosen as
outlined in Load-Line Regulation Resistor. Select a target
bandwidth for the compensated system, f₀. The target
bandwidth must be large enough to assure adequate
transient performance, but smaller than 1/3 of the per-
channel switching frequency. The values of the
compensation components depend on the relationships of f₀
to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
of equations for the compensation components.
Case 1:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----p---p--------L---C---}
0.75 V _{I N}
C_C
=
--------0---.--7---5----V----^I--^N---------
2πV_PPR_FBf₀
.
Case 2:
---------1----------
2π LC
≤
f₀
<
--------------1---------------
2πC(ESR)
R_C
=
R_FB
V-----_P----P----(_--2----π_----)_--²_----f--0--²_{----L----C---}
0.75 V_IN
C_C
=
--------------------0----.-7----5---V-----^I--^N---------------------
(2π)² f₀₂ V_PPR_FB LC
(EQ. 24)
Case 3:
f₀
>
--------------1---------------
2πC(ESR)
R_C
=
R_FB
--------2----^π----f--⁰---V-----^p---^p---L---------
0.75 V_IN (ESR)
C_C
=
-0---.--7---5----V----^I--^N----⁽--E-----S----R-----⁾-------C---
2πV_PPR_FBf₀ L
In Equations 24, L is the per-channel filter inductance
divided by the number of active channels; C is the sum total
of all output capacitors; ESR is the equivalent-series
resistance of the bulk output-filter capacitance; and V_PP is
the peak-to-peak sawtooth signal amplitude as described in
Figure 16 and Electrical Specifications.
C₂
R_C ^CC
COMP
C₁
R₁
R_FB
FB
IOUT
VDIFF
FIGURE 26. COMPENSATION CIRCUIT FOR ISL6244 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
Once selected, the compensation values in Equations 24
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equations 24 unless some performance issue is noted.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 25). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading edge jitter problem is noted.
19
FN9106.3
December 28, 2004