ISL6123_11 Datasheet, PDF (20/23 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
Negative Voltage Sequencing
The ISL612X family can use the charged pump GATE output to
drive FETs that would control and sequence negative voltages
down to a nominal -5V with minimal additional external circuitry.
Figure 24 shows simultaneous turn-on of the 5V bipolar supplies,
and then simultaneous turn-off of the +2.5V and both positive
supplies after the -5V. Figure 25 shows the minimal additional
external circuitry to accomplish this. The 5V zener diode is used
to level-shift the GATE drive down by 5V to prevent premature
turn-on when GATE = 0V. Once GATE drive voltage > Vz, then FET
Vgs > 5V, ensuring full turn-on once GATE gets to VDD + 5.3V.
Turn-on and turn-off ramp rates can be adjusted with the FET
gate series resistor value. The -V rail is sequenced normally via
the DLY_X capacitor value, although adjustments in prototyping
should be factored in to fine-tune for actual circuit requirements.
Figures 26 and 27 illustrate a high-accuracy -V detection circuit
using the ISL6131 and a low-cost, low-accuracy -V detection
circuit, respectively.
FIGURE 24. ±VOLTAGE SEQUENCING
-V_IN
-V_OUT
R1
ISL612X GATE
ADDITIONAL 2 COMPONENTS
D1
NECESSARY FOR -V CONTROL
AND SEQUENCING.
D1 necessary to prevent premature turn-on. R1 is used to hold
FET Vgs = 0V until D1 Vz is overcome. R1 value can be changed to
adjust -V ramp rates. Choose an R1 value between 4MW and 10MW
initially, and fine-tune resistor value for the particular need.
+V
R1
+BIAS
R3
(1k)
ISL6131
VMON
OR
R2
ISL6536A _PGOOD R4
(15K)
-BIAS
-V
R5
(10k)
Q1 Si1300DL
OR EQUIV.
TO UVLO OF
ISL612X FOR
R6 ^{-V CONTROL AND}
SEQUENCING
R1 and R2 define -V UVLO level.
R3 ensures supervisor (ISL6131 or ISL6536A) PGOOD pull-up.
R4 and R5 provide Q1 gate bias between 0V and +V
to 0V (resistor values suitable for -V = -5V and +V = +3.3V).
FIGURE 26. HIGH ACCURACY -V LOCK OUT
+V
R1
R2
-V
TO UVLO OF ISL612X FOR CONTROL
AND SEQUENCING OF -V
Choose R1 and R2 values to drive UVLO
high when -V is sufficiently present.
FIGURE 27. LOW ACCURACY -V PRESENCE DETECTION
Application Considerations
Timing Error Sources
In any system there are variance contributors. For the ISL612x
family, timing errors are mainly contributed by three sources.
Capacitor Timing Mismatch Error
Obviously, the absolute capacitor value is an error source; thus,
lower-percentage tolerance capacitors help to reduce this error
source. Figure 28 illustrates a difference of 0.57ms between two
DLY_X outputs ramping to DLY_X threshold voltage. These 5%
capacitors were from a common source. In applications where
two or more GATEs or LOGIC outputs must have concurrent
transitions, it is recommended that a common GATE drive be
used to eliminate this timing error.
FIGURE 25. -VOLTAGE FET DRIVE CIRCUIT
FIGURE 28. CAPACITOR TIMING MISMATCH
20
FN9005.11
August 25, 2011