ISL6123_11 Datasheet, PDF (18/23 Pages) Intersil Corporation – Power Sequencing Controllers

ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128, ISL6130
ISL6131 or ISL6132
MONITORING
ON ALL RAILS
PGOOD
VMON
en
OE
LOW = RESET
SYSRST
ISL6124
#N
G
UVLO
A
T
RESET
E
ENABLE
RESET
POWER
SUPPLY
ENABLE
SYSRST
ISL6125 _L
# N+1 _O
G
RESET
I
UVLO
C
UVLO
en
RESET
POWER
SUPPLY
OE
LOW = RESET
SYSRST
ISL6124
#N
G
UVLO
A
T
RESET
E
ENABLE
ENABLE
SYSRST
ISL6125 _L
# N+1 _O
RESET
G
I
UVLO
C
FIGURE 19. ISL612X AND ISL613X VOLTAGE COMPLIANT
SEQUENCING BLOCK DIAGRAM
If the mere presence of some voltage potential is adequate prior
to sequencing on, then a small number of standard logic AND
gates can be used to accomplish this. The block diagram in
Figure 20 illustrates this voltage presence configuration.
In either case, the sequencing is straightforward across multiple
sequencers, as all DLY_ON capacitors simultaneously start
charging ~10ms after the common ENABLE input signal is
delivered. This allows the choice of capacitors to be related to
each other and is no different than using a single sequencer.
When the common enabling signal is de-asserted, these
configurations execute the turn-off sequence across all
sequencers as programmed by the DLY_OFF capacitor values.
In both cases, with all the SYSRST pins bused together, once the
turn-on sequence is complete, simultaneous shutdown upon any
UVLO input failure is assured. SYSRST output momentarily pulls
low and turns off all GATE and LOGIC outputs.
Some applications may require or allow groups of supplies to be
brought up in sequence and for supplies within each group to be
sequenced. Figure 21 shows a configuration that allows the first
group of supplies to turn on before the second group starts. This
arrangement does not necessarily preclude adding the
assurance of all supplies prior to turn-on sequencing, as
previously shown. It does prevent the turn-on sequence from
completing, if there is one unsatisfied UVLO input in a group.
This configuration involves waiting through the T_UVLOdel and
T_RSTdel (total of ~160ms) for each sequencer IC in the chain
before the final RESET releases. Once ENABLE on the first
sequencer is de-asserted, all RESET outputs quickly pull low. This
FIGURE 20. MULTIPLE ISL612X USING LOGIC GATES FOR
VOLTAGE PRESENCE DETECT
allows the sequenced turn-off of this configuration to ripple
through several banks as quickly as the user-programmed (by
DLY_OFF) sequence capacitors allow.
Again, with common bused SYSRTS pins, simultaneous
shutdown of all GATEs and LOGIC down upon an unsatisfied UVLO
input is assured, once all FETs or LOGIC outputs are on. If a GATE
drive option IC is used to drive both FETs and logic signals, then
care must be taken to ensure the charged pump GATE does not
overdrive and damage the logic input. A simple resistor divider
can be used to lower the GATE to a suitable voltage for the logic
input, as shown in Figure 21.
18
FN9005.11
August 25, 2011