ISL6446 Datasheet, PDF (2/20 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

Pin Configuration
ISL6446
ISL6446
(24 LD QSOP)
TOP VIEW
OCSET1 1
SS1/EN1 2
COMP1 3
FB1 4
RT 5
SGND 6
LCDR 7
LCFB 8
FB2 9
COMP2 10
SS2/EN2 11
OCSET2 12
24 VIN
23 BOOT1
22 UGATE1
21 PHASE1
20 LGATE1
19 VCC
18 PGND
17 LGATE2
16 PHASE2
15 UGATE2
14 BOOT2
13 PGOOD
Pin Descriptions
SYMBOL PIN #
DESCRIPTION
BOOT1, 2 23, 14 These pins power the upper MOSFET drivers of each PWM converter. The anode of each internal bootstrap diode is connected
to the VCC pin. The cathode of the bootstrap diode is connected to this pin, which should also connect to the bootstrap capacitor.
UGATE1, 2 22, 15 These pins provide the gate drive for upper MOSFETs, bootstrapped from the VCC pin.
PHASE1, 2 21, 16 These are the junction points of the upper MOSFET sources, output filter inductor and lower MOSFET drains. Connect these pins
accordingly to the respective converter.
LGATE1, 2 20, 17 These are the outputs of the lower N-Channel MOSFET drivers, sourced from the VCC pin.
PGND
18 This pin provides the power ground connection for the lower gate drivers. This pin should be connected to the source of the lower
MOSFET for PWM1 and PWM2 and the negative terminals of the external input capacitors.
FB1, 2
4, 9 These pins are connected to the feedback resistor divider and provide the voltage feedback signals for the respective controller. They
set the output voltage of the converter. In addition, the PGOOD circuit and OVP circuit use these inputs to monitor the output voltage
status.
COMP1, 2 3, 10 These pins are the error amplifier outputs for the respective PWM. They are used, along with the FB pins, as the compensation point
for the PWM error amplifier.
PGOOD
13 This is an open drain logic output used to indicate the status of the output voltages. This pin is pulled low when either of the two
PWM outputs is not within 10% of the respective nominal voltage or when the linear output drops below 75% of its nominal voltage.
To maintain the PGOOD function if the linear output is not used, connect LCFB to VCC.
SGND
6 This is the signal ground, common to both controllers, and must be routed separately from the high current grounds (PGND). All
voltage levels are measured with respect to this pin.
VIN
24 This pin powers the controllers with an internal linear regulator (if VIN > 5.5V) and must be closely decoupled to ground using a
ceramic capacitor as close to the VIN pin as possible. VIN is also the input voltage applied to the upper FET of both converters.
TABLE 1. INPUT SUPPLY CONFIGURATION
INPUT
PIN CONFIGURATION
5.5V to 24V
Connect the input supply to the VIN pin. The VCC
pin will provide a 5V output from the internal
voltage regulator.
5V ±10%
Connect the input supply to the VCC pin.
VCC
19 This pin supplies the bias for the regulators, powers the low side gate drivers and external boot circuitry for high side gate drivers.
The IC may be powered directly from a single 5V (±10%) supply at this pin; when used as a 5V supply input, this pin must be
externally connected to VIN. When VIN > 5.5, VCC is the output of the internal 5V linear regulator output. The VCC pin must always
be decoupled to power ground with a minimum of 1µF ceramic capacitor, placed very close to the pin.
2
FN7944.0
July 10, 2012