ISL6446 Datasheet, PDF (18/20 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
V_IN
ISL6446
UGATE
PHASE
LGATE
PGND
Q1
L_OUT
V_OUT
C_IN
Q2
C_OUT
RETURN
FIGURE 28. PRINTED CIRCUIT BOARD POWER AND GROUND
PLANES OR ISLANDS
C_VCC
R_RT C_SS
VCC
BOOT
C_{BOOT CIN}
ISL6446
SS ^PHASE
RT
VIN
+V_IN
SGND PGND
C_VIN
SGND
+V_IN
Q1 _LOUT
V_OUT
Q2 ^COUT
PGND
Figure 29 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction for
the circuits shown. Locate the RT resistor as close as possible to
the RT pin and the SGND pin. Provide local decoupling between
VCC and GND pins.
For each switcher, minimize any leakage current paths on the
SS/EN pin and locate the capacitor, C_SS close to the SS/EN pin
because the internal current source is only 30µA. All of the
compensation network components for each switcher should be
located near the associated COMP and FB pins. Locate the
capacitor, C_BOOT as close as practical to the BOOT and PHASE
pins (but keep the noisy PHASE plane away from the IC (except
for the PHASE pin connection).
The OCSET circuits (see Figure 4 on page 5) should have a
separate trace from the upper FET to the OCSET R and C; that will
more accurately sense the VIN at the FET than just tying them to
the VIN plane. The OCSET R and C should be placed near the IC
pins.
FIGURE 29. PRINTED CIRCUIT BOARD POWER AND GROUND
PLANES OR ISLANDS
18
FN7944.0
July 10, 2012