ISL6446 Datasheet, PDF (15/20 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
provide either 0% or 100% duty cycle in response to a load
transient. The response time is the time required to slew the
inductor current from an initial current value to the transient
current level. During this interval, the difference between the
inductor current and the transient current level must be supplied
by the output capacitor. Minimizing the response time can
minimize the output capacitance required.
The response time to a transient is different for the application of
load and the removal of load. The following equations give the
approximate response time interval for application and removal
of a transient load:
t_RISE
=
L_{----O-----U----T-----}×_----I_{--T----R----A----N--}
V_IN – V_OUT
(EQ. 9)
t_FALL
=
L_{----O-----U----T----}×_-----I_{--T----R----A----N--}
V_OUT
(EQ. 10)
where: I_TRAN is the transient load current step, t_RISE is the
response time to the application of load, and t_FALL is the
response time to the removal of load. With a +5V input source,
the worst case response time can be either at the application or
removal of load and dependent upon the output voltage setting.
Be sure to check both of these equations at the minimum and
maximum output levels for the worst case response time.
Finally, check that the inductor I_sat rating is sufficiently above the
maximum output current (DC load plus ripple current).
OUTPUT CAPACITOR SELECTION
An output capacitor is required to filter the output and supply the
load transient current. The filtering requirements are a function
of the switching frequency and the ripple current. The load
transient requirements are a function of the slew rate (di/dt) and
the magnitude of the transient load current. These requirements
are generally met with a mix of capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors. The
bulk filter capacitor values are generally determined by the ESR
(effective series resistance) and voltage rating requirements
rather than actual capacitance requirements.
High frequency decoupling capacitors should be placed as close to
the power pins of the load as physically possible. Be careful not to
add inductance in the circuit board wiring that could cancel the
usefulness of these low inductance components. Consult with the
manufacturer of the load on specific decoupling requirements. Keep
in mind that not all applications have the same requirements; some
may need many ceramic capacitors in parallel; others may need
only one.
Use only specialized low-ESR capacitors intended for switching-
regulator applications for the bulk capacitors. The bulk
capacitor’s ESR will determine the output ripple voltage and the
initial voltage drop after a high slew-rate transient. An aluminum
electrolytic capacitor's ESR value is related to the case size with
lower ESR available in larger case sizes. However, the equivalent
series inductance (ESL) of these capacitors increases with case
size and can reduce the usefulness of the capacitor to high slew-
rate transient loading. Unfortunately, ESL is not a specified
parameter. Work with your capacitor supplier and measure the
capacitor’s impedance with frequency to select a suitable
component. In most cases, multiple electrolytic capacitors of
small case size perform better than a single large case capacitor.
INPUT CAPACITOR SELECTION
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic capacitors for
high frequency decoupling and bulk capacitors to supply the
current needed each time Q1 (upper FET) turns on. Place the
small ceramic capacitors physically close to the MOSFETs and
between the drain of Q1 and the source of Q2 (lower FET).
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable operation,
select the bulk capacitor with voltage and current ratings above
the maximum input voltage and largest RMS current required by
the circuit. The capacitor voltage rating should be at least 1.25
times greater than the maximum input voltage and a voltage
rating of 1.5 times is a conservative guideline. The RMS current
rating requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
SWITCHER MOSFET SELECTION
V_IN for the ISL6446 has a wide operating voltage range allowed,
so both FETs should have a source-drain breakdown voltage (V_DS)
above the maximum supply voltage expected; 20V or 30V are
typical values available.
The ISL6446 gate drivers (UGATE_x and LGATE_x) were designed to
drive single FETs (for up to ~10A of load current) or smaller dual
FETs (up to 4A). Both sets of drivers are sourced by the internal VCC
regulator (unless V_IN = V_CC = 5V, in which case the gate driver
current comes from the external 5V supply). The maximum current
of the regulator (I_{CC_max)} is listed in the “Electrical Specifications”
Table on page 6; this may limit how big the FETs can be. In addition,
the power dissipation of the regulator is a major contributor to the
overall IC power dissipation (especially as C_in of the FET or V_IN or
F_SW increases).
Since V_CC is around 5V, that affects the FET selection in two
ways. First, the FET gate-source voltage rating (V_GS) can be as
low as 12V (this rating is usually consistent with the 20V or 30V
breakdown chosen above). Second, the FETs must have a low
threshold voltage (around 1V), in order to have its r_DS(ON) rating
at V_GS = 4.5V in the 10mΩ to 40mΩ range that is typically used
for these applications. While some FETs are also rated with gate
voltages as low as 2.7V, with typical thresholds under 1V, these
can cause application problems. As LGATE shuts off the lower
FET, it does not take much ringing in the LGATE signal to turn the
lower FET back on, while the Upper FET is starting to turn on,
causing some shoot-through current. Therefore, avoid FETs with
thresholds below 1V.
If the power efficiency of the system is important, then other FET
parameters are also considered. Efficiency is a measure of power
losses from input to output, and it contains two major
components: losses in the IC (mostly in the gate drivers) and
losses in the FETs. For low duty cycle applications (such as 12V in
to 1.5V out), the upper FET is usually chosen for low gate charge,
since switching losses are key, while the lower FET is chosen for
low r_DS(ON), since it is on most of the time. For high duty cycles
(such as 5.0V in to 3.3V out), the opposite may be true.
15
FN7944.0
July 10, 2012