ISL6446 Datasheet, PDF (17/20 Pages) Intersil Corporation – Dual (180° Out-of-Phase) PWM and Linear Controller

ISL6446
2. Calculate C1 such that F_Z1 is placed at a fraction of the F_LC, at 0.1
to 0.75 of F_LC (to adjust, change the 0.5 factor to desired
number). The higher the quality factor of the output filter and/or
the higher the ratio F_CE/F_LC, the lower the F_Z1 frequency (to
maximize phase boost at F_LC).
C1
=
-----------------------¹------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ F_LC
(EQ. 14)
3. Calculate C2 such that F_P1 is placed at F_CE.
C2
=
-------------------------^C-----¹---------------------------
2π ⋅ R2 ⋅ C1 ⋅ F_CE – 1
(EQ. 15)
4. Calculate R3 such that F_Z2 is placed at F_LC. Calculate C3 such
that F_P2 is placed below F_SW (typically, 0.5 to 1.0 times F_SW).
F_SW represents the switching frequency. Change the
numerical factor to reflect desired placement of this pole.
Placement of F_P2 lower in frequency helps reduce the gain of
the compensation network at high frequency, in turn reducing
the HF ripple component at the COMP pin and minimizing
resultant duty cycle jitter.
R3
=
--------^R----¹---------
F_{----S----W----}
F_LC
–
1
C3 = -₂---_π-----_â‹---_R-----₃-----_â‹--¹-₀---_.--₇-----_â‹---_F----_S---_W----
(EQ. 16)
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error amplifier’s
open-loop gain. Verify phase margin results and adjust as
necessary. The following equations describe the frequency
response of the modulator (G_MOD), feedback compensation
(G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
--------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
1 + s(f) ⋅ (E + D) ⋅ C + s²(f) ⋅ L ⋅ C
(EQ. 17)
G_FB(f)
=
-----¹-----+-----^s----⁽--^f--⁾----^â‹---^R----²-----^â‹---^C-----¹-------
s(f) ⋅ R1 ⋅ (C1 + C2)
⋅
⋅ -------------------------------¹-----+-----^s---⁽--^f---⁾---^â‹---⁽---^R----¹-----+-----^R-----³----⁾---^â‹---^C-----³--------------------------------
(
1
+
s
(f)
⋅
R
3
⋅
C
3)
⋅
⎝⎛¹
+
s(f)
⋅
R2
⋅
⎛
⎝
C^-C----1^{-1----+-⋅---C-}C^----2-2^{--⎠⎞ ⎠⎞}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where:
s(f) = 2π ⋅ f ⋅ j
(EQ. 18)
(EQ. 19)
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
---------------¹----------------
2π ⋅ R2 ⋅ C1
(EQ. 20)
F_Z2
=
-------------------------¹--------------------------
2π ⋅ (R1 + R3) ⋅ C3
(EQ. 21)
F_P1 = ₂----_π-----_â‹---_R-----₂-----_⋹---_{C--C--------1--1--------+-â‹}------_C--_C--------₂--₂----
F_P2
=
---------------¹----------------
2π ⋅ R3 ⋅ C3
(EQ. 22)
(EQ. 23)
Figure 27 shows an asymptotic plot of the DC/DC converter’s gain vs
frequency. The actual Modulator Gain has a high gain peak
dependent on the quality factor (Q) of the output filter, which is not
shown. Using the previously mentioned guidelines should yield a
compensation gain similar to the curve plotted. The open loop error
amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the log-log
graph of Figure 27 by adding the modulator gain, G_MOD (in dB), to
the feedback compensation gain, G_FB (in dB). This is equivalent to
multiplying the modulator transfer function and the compensation
transfer function and then plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20 log
⎛
⎝
RR-----21--_⎠⎞
0
LOG
20log ^d----^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
G_FB
G_CL
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 27. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of the
switching frequency, F_SW.
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another can
generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
Figure 28 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of ground or power plane
in a printed circuit board. The components shown in Figure 28
should be located as close together as possible. Please note that
the capacitors C_IN and C_OUT each represent numerous physical
capacitors. Locate the ISL6446 within 1 inch of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6446 must be sized to handle up to 2A
peak current.
17
FN7944.0
July 10, 2012