ISL23315_11 Datasheet, PDF (2/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer

Block Diagram
V_LOGIC
ISL23315
V_CC
SCL
SDA
A1
A0
I/O
BLOCK
LEVEL
SHIFTER
Pin Configurations
ISL23315
(10 LD MSOP)
TOP VIEW
V_LOGIC
1
SCL
2
SDA
3
A0
4
A1
5
10 GND
9
V_CC
8
RH
7
RW
6
RL
ISL23315
(10 LD µTQFN)
TOP VIEW
SCL 1
SDA 2
A0 ₃
A1 ₄
9 ^GND
8 ^VCC
7 ^RH
6 ^RW
POWER-UP
R_H
INTERFACE,
CONTROL
AND
STATUS
WR
VOLATILE
REGISTER
LOGIC
AND
WIPER
CONTROL
CIRCUITRY
R_L
R_W
GND
Pin Descriptions
MSOP
1
µTQFN
10
2
1
3
2
4
3
5
4
6
5
7
6
8
7
9
8
10
9
SYMBOL
V_LOGIC
DESCRIPTION
I²C bus /logic supply. Range 1.2V to
5.5V
SCL Logic Pin - Serial bus clock input
SDA Logic Pin - Serial bus data
input/open drain output
A0 Logic Pin - Hardwire slave address
pin for I²C serial bus.
Range: V_LOGIC or GND
A1 Logic Pin - Hardwire slave address
pin for I²C serial bus.
Range: V_LOGIC or GND
RL DCP “low” terminal
RW DCP wiper terminal
RH DCP “high” terminal
V_CC Analog power supply.
Range 1.7V to 5.5V
GND Ground pin
2
FN7778.1
August 15, 2011