ISL23315_11 Datasheet, PDF (14/20 Pages) Intersil Corporation – Single, Low Voltage Digitally Controlled Potentiometer

ISL23315
DEVICE ADDRESS (A1, A0)
The address inputs are used to set the least significant 2 bits of
the 7-bit I²C interface slave address. A match in the slave
address serial data stream must match with the Address input
pins in order to initiate communication with the ISL23315. A
maximum of four ISL23315 devices may occupy the I²C serial
bus (see Table 3).
V_LOGIC
This is an input pin, that supplies internal level translator for
serial bus operation from 1.2V to 5.5V.
Principles of Operation
The ISL23315 is an integrated circuit incorporating one DCP with
its associated registers and an I²C serial interface providing
direct communication between a host and the potentiometer.
The resistor array is comprised of individual resistors connected
in series. At either end of the array and between each resistor is
an electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make before
break” mode when the wiper changes tap positions.
Voltage at any DCP pins, R_H, R_L or R_W, should not exceed V_CC
level at any conditions during power-up and normal operation.
The V_LOGIC pin needs to be connected to the I²C bus supply
which allows reliable communication with the wide range of
microcontrollers and independent of the V_CC level. This is
extremely important in systems where the master supply has
lower levels than DCP analog supply.
DCP Description
The DCP is implemented with a combination of resistor elements
and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin of the DCP is connected to
intermediate nodes, and is equivalent to the wiper terminal of a
mechanical potentiometer. The position of the wiper terminal
within the DCP is controlled by an 8-bit volatile Wiper Register
(WR). When the WR of a DCP contains all zeroes (WR[7:0]= 00h),
its wiper terminal (RW) is closest to its “Low” terminal (RL). When
the WR register of a DCP contains all ones (WR[7:0]= FFh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As the
value of the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time, the
resistance between RW and RL increases monotonically, while
the resistance between RH and RW decreases monotonically.
While the ISL23315 is being powered up, the WR is reset to 80h
(128 decimal), which locates RW roughly at the center between
R_L and R_H.
The WR can be read or written to directly using the I²C serial
interface as described in the following sections.
Memory Description
The ISL23315 contains two volatile 8-bit registers: Wiper Register
(WR) and Access Control Register (ACR). The memory map of
ISL23315 is shown in Table 1. The Wiper Register (WR) at address 0
contains current wiper position. The Access Control Register (ACR)
at address 10h contains information and control bits described
in Table 2.
ADDRESS
(hex)
10
0
TABLE 1. MEMORY MAP
VOLATILE
REGISTER NAME
DEFAULT SETTING
(hex)
ACR
40
WR
40
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT # 7
6
5
4
3
2
1
0
NAME/ 0 SHDN 0 0
0
0
0
0
VALUE
Shutdown Function
The SHDN bit (ACR[6]) disables or enables shutdown mode for all
DCP channels simultaneously. When this bit is 0, i.e., DCP is forced
to end-to-end open circuit and RW is connected to RL through a
2kΩ serial resistor, as shown in Figure 25. Default value of the
SHDN bit is 1.
RH
RW
2kΩ
RL
FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE
In the shutdown mode, the RW terminal is shorted to the RL
terminal with around 2kΩ resistance, as shown in Figure 25. When
the device enters shutdown, all current DCP WR settings are
maintained. When the device exits shutdown, the wipers will return
to the previous WR settings after a short settling time (see
Figure 26).
In shutdown mode, if there is a glitch on the power supply which
causes it to drop below 1.3V for more than 0.2µs to 0.4µs, the
wipers will be RESET to their mid position. This is done to avoid
an undefined state at the wiper outputs.
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FN7778.1
August 15, 2011