82C83H Datasheet, PDF(2/6 Page) Intersil Corporation – CMOS Octal Latching Inverting Bus Driver

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82C83H Datasheet, PDF (2/6 Pages) Intersil Corporation – CMOS Octal Latching Inverting Bus Driver

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82C83H

Functional Diagram

DI0

CLK

DI1

DI2

DI3

DI4

DI5

DI6

DI7

STB

state). The 82C8X series gated inputs mean that this condi-

tion will occur only during the time the device is in the trans-

parent mode (STB = logic one). ICC remains below the

DO0

maximum ICC standby speciï¬cation of 10ÂµA during the time

inputs are disabled, thereby greatly reducing the average

power dissipation of the 82C8X series devices.

DO1

DO2

DO3

DO4

DO5

DO6

DO7

DATA IN

VCC

INTERNAL

DATA

Gated Inputs

During normal system operation of a latch, signals on the

bus at the device inputs will become high impedance or

make transitions unrelated to the operation of the latch.

These unrelated input transitions switch the input circuitry

and typically cause an increase in power dissipation in

CMOS devices by creating a low resistance path between

VCC and GND when the signal is at or near the input switch-

ing threshold. Additionally, if the driving signal becomes high

impedance (``ï¬oat'' condition), it could create an indetermi-

nate logic state at the inputs and cause a disruption in

device operation.

The Intersil 82C8X series of bus drivers eliminates these

conditions by turning off data inputs when data is latched

(STB = logic zero for the 82C82/83H) and when the device is

disabled (OE = logic one for the 82C86H/87H). These gated

inputs disconnect the input circuitry from the VCC and

ground power supply pins by turning off the upper P-channel

and lower N-channel (See Figures 1 and 2). No current ï¬ow

from VCC to GND occurs during input transitions and invalid

logic states from ï¬oating inputs are not transmitted. The next

stage is held to a valid logic level internal to the device.

STB

DATA IN

VCC

INTERNAL

DATA

FIGURE 1. 82C82/83H

FIGURE 2. 82C86H/87H GATED INPUTS

Decoupling Capacitors

The transient current required to charge and discharge the

300pF load capacitance speciï¬ed in the 82C83H data sheet

is determined by

I = CL (dv/dt)

Assuming that all outputs change state at the same time and

that dv/dt is constant;

I = CL(--V-----C----C------Ã-----8t-R--0----â--t-p-F---e----r--c----e----n---t---)

(EQ. 1)

where tR = 20ns, VCC = 5.0V, CL = 300pF on each eight out-

puts.

I = (8 x 300 x 10-12) x (5.0V x 0.8)/(20 x 10-9) = 480mA

This current spike may cause a large negative voltage spike on

VCC which could cause improper operation of the device. To ï¬l-

ter out this noise, it is recommended that a 0.1ÂµF ceramic disc

capacitor be placed between VCC and GND at each device,

with placement being as near to the device as possible.

ALE

MULTI-

PLEXED

BUS

ICC

ADDRESS

STB

DATA IN

VCC

INTERNAL

DATA

D.C. input voltage levels can also cause an increase in ICC if

these input levels approach the minimum VIH or maximum

VIL conditions. This is due to the operation of the input cir-

cuitry in its linear operating region (partially conducting

FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS

4-282

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