ISL78200_14 Datasheet, PDF (19/22 Pages) Intersil Corporation – 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78200
Phase margin: 45°
The compensator design procedure is as follows:
1. Position _CZ2 and _CP to derive R3 and C3.
Put the compensator zero _CZ2 at (1 to 3)/(R_oC_o)
_cz2
=
------³-------
R_oC_o
(EQ. 26)
Put the compensator pole _CP at ESR zero or 0.35 to 0.5 times
of switching frequency, whichever is lower. In all-ceramic-cap
design, the ESR zero is normally higher than half of the switching
frequency. R3 and C3 can be derived as following:
Case A: ESR zero
---------¹-----------
2R_cC_o
less than (0.35 to 0.5)f_s
C₃
=
R_-----o---C_{----o----–----}3_----R_----c---C_----o-
3R₁
R₃
=
---³----^R----^c---^R----¹----
R_o – 3R_c
Case B: ESR zero ₂----_----_R-¹---_c---_C----_o- larger than (0.35 to 0.5)f_s
(EQ. 27)
(EQ. 28)
C₃
=
0_----._-3_----3_----R_----o---C_----o---f_{--s----–-----}0_---._--4_---6_--
f_sR₁
R₃
=
-----------------^R----¹-------------------
0.73R_oC_of_s – 1
(EQ. 29)
(EQ. 30)
Case C: Derive at R2 and C1.
The loop gain L_v(S) at cross over frequency of f_c has unity gain.
Therefore, C1 is determined by Equation 31.
C₁
=
-^--^R----¹-----+-----^R----³---^---^C---³--
2
f_c
R_t
R₁
C
o
(EQ. 31)
The compensator zero _CZ1 can boost the phase margin and
bandwidth. To put _CZ1 at 2 times of cross cover frequency f_c is a
good start point. It can be adjusted according to specific design.
R1 can be derived from Equation 32.
R₂
=
---------¹---------
4f_cC₁
(EQ. 32)
Example: V_IN = 12V, V_o = 5V, I_o = 2A, fs = 500kHz,
C_o = 60µF/3m, L = 10µH, R_t = 0.20V/A, f_c = 50kHz,
R1 = 105k, R_BIAS = 20k.
Select the crossover frequency to be 35kHz. Since the output
capacitors are all ceramics, use Equation 29 and 30 to derive R3
to be 20k and C3 to be 470pF.
Then use Equation 31 and 32 to calculate C1 to be 180pF and
R2 to be 12.7k. Select 150pF for C1 and 15k for R2.
There is approximately 30pF parasitic capacitance between
COMP to FB pins that contributes to a high frequency pole.
Figure 34 shows the simulated bode plot of the loop. It is shown
that it has 26kHz loop bandwidth with 70° phase margin and
-28dB gain margin.
80
60
40
20
0
-20
-40
-60
100
LOOP GAIN
1k
10k
100k
1M
FREQUENCY (Hz)
PHASE MARGIN
180
160
140
120
100
80
60
40
20
0100
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 34. SIMULATED LOOP BODE PLOT
Note in applications where the PFM mode is desired especially
when type III compensation network is used, the value of the
capacitor between the COMP pin and the FB pin (not the
capacitor in series with the resistor between COMP and FB)
should be minimal to reduce the noise coupling for proper PFM
operation. No external capacitor between COMP and FB is
recommended at PFM applications.
Boost Inductor
Besides the need to sustain the current ripple to be within a
certain range (30% to 50%), the boost inductor current at its
soft-start is a more important perspective to be considered in
selection of the boost inductor. Each time the boost starts up,
there is a fixed 500µs soft-start time when the duty cycle
increase linearly from t_MINON to ~50%. Before and after boost
start-up, the boost output voltage will jump from V_IN_boost to
voltage (V_IN_boost+V_OUT_buck). The design target in boost
soft-start is to ensure the boost input current is sustained to a
minimum but capable of charging the boost output voltage to
have a voltage step equaling to V_OUT_buck. A big inductor will
block the inductor current increase and not high enough to be
able to charge the output capacitor to the final steady state value
(V_IN_boost+V_OUT_buck) within 500µs. A 6.8µH inductor is a good
starting point for its selection in design. The boost inductor
current at start-up must be checked by an oscilloscope to ensure
19
FN7641.2
December 24, 2013