ISL78200_14 Datasheet, PDF (13/22 Pages) Intersil Corporation – 2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter

ISL78200
Functional Description
Initialization
Initially, the ISL78200 continually monitors the voltage at EN pin.
When the voltage on EN pin exceeds its rising threshold, the
internal LDO will start-up to build up V_CC. After Power-On Reset
(POR) circuits detect that V_CC voltage has exceeded the POR
threshold, the soft-start will be initiated.
Soft-Start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5µA current source.
C_SSF = 6.5  t_SSS
(EQ. 1)
The SS ramp starts from 0V to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and the IC goes
into steady state operation.
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at overload
condition. When a harsh condition occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At the dummy SS cycle, the current to charge the
soft-start cap is cut down to 1/5 of its normal value. Therefore, a
dummy SS cycle takes 5 times that of the regular SS cycle.
During the dummy SS period, the control loop is disabled and no
PWM output. At the end of this cycle, it will start the normal SS.
The hiccup mode persists until the second overcurrent threshold
is no longer reached.
The ISL78200 is capable of start-up with prebiased output.
PWM Control
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL78200 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
“Block Diagram” on page 4.
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is triggered to shut down the PWM
logic to turn off the high-side MOSFET. The high-side MOSFET
stays off until the next clock signal comes for the next cycle.
The output voltage is sensed by a resistor divider from V_OUT to the
FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
PFM Mode Operation
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL78200 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. This
threshold is 700mA as default when there is no programming
resistor at MODE pin. It can also be programmed by a resistor at
the MODE pin to ground (see Equation 2).
R_MODE
=
-----¹---¹----⁸---⁵----⁰---⁰------
IPFM + 0.2
(EQ. 2)
where IPFM is the desired PWM/PFM boundary current threshold
and R_MODE is the programming resistor.
500
400
300
200
100
0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
IPFM (A)
FIGURE 28. R_MODE vs IPFM
Synchronous and
Non-Synchronous Buck
The ISL78200 supports both synchronous and non-synchronous
buck operations. For a non-synchronous buck operation when a
power diode is used as the low-side power device, the LGATE
driver can be disabled with LGATE connected to VCC (before IC
start-up).
AUXVCC Switch-Over
The ISL78200 has an auxiliary LDO integrated as shown in the
block diagram. It is used to replace the internal MAIN LDO
function after the IC start-up. “Typical Application Schematic II -
V_CC Switch Over to V_OUT” on page 5 shows its basic application
setup with output voltage connected to AUXVCC. After IC
soft-start done and the output voltage is built up to steady state,
once the AUXVCC pin voltage is over the AUX LDO Switch-over
Rising Threshold, the MAIN LDO is shut off and the AUXILIARY
LDO is activated to bias VCC. Since the AUXVCC pin voltage is
lower than input voltage V_IN, the internal LDO dropout voltage
and the consequent power loss is reduced. This feature brings
substantial efficiency improvements in light load range
especially at high input voltage applications.
When the voltage at AUXVCC falls below the AUX LDO Switch-over
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
13
FN7641.2
December 24, 2013