ISL6142 Datasheet, PDF (19/23 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6142, ISL6152
be found, then consider 2 separate resistor dividers (one for
each pin, both from V_DD to -V_IN). This also allows the user to
adjust or trim either trip point independently. Some
applications employ a short pin ground on the connector tied
to R4 to ensure the hot plug device is fully powered up
before the UV and OV pins (tied to the short pin ground) are
biased. This ensures proper control of the GATE is
maintained during power up. This is not a requirement for the
ISL6142/52 however the circuit will perform properly if a
short pin scheme is implemented (reference Figure 38).
Applications: PWRGD/PWRGD
The PWRGD/PWRGD outputs are typically used to directly
enable a power module, such as a DC/DC converter. The
PWRGD (ISL6142) is used for modules with active low
enable (L version), and PWRGD (ISL6152) for those with an
active high enable (H version). The modules usually have a
pull-up device built-in, as well as an internal clamp. If not, an
external pull-up resistor may be needed. If the pin is not
used, it can be left open.
For both versions at initial start-up, when the DRAIN to V_EE
voltage differential is less than 1.3V and the GATE voltage is
within 2.5V (V_GH) of its normal operating voltage (13.6V),
power is considered good and the PWRGD/PWRGD pins
will go active. At this point the output is latched and the
comparators above no longer control the output. However a
second DRAIN comparator remains active and will drive the
PWRGD/PWRGD output inactive if the DRAIN voltage
exceeds V_EE by more than 8V. The latch is reset by any of
the signals that shut off the GATE (Over-Voltage, Under-
Voltage; Under-Voltage-Lock-Out; Over-Current Time-Out,
disable pin high, or powering down). In this case the
PWRGD/PWRGD output will go inactive, indicating power is
no longer good.
ISL6142 (L version; Figure 34): Under normal conditions
(DRAIN voltage - V_EE < V_PG, and ∆V_GATE - V_GATE < V_GH)
the Q2 DMOS will turn on, pulling PWRGD low, enabling the
module.
When any of the 5 conditions occur that turn off the GATE
(OV, UV, UVLO, Over-Current Time-Out, disable pin high)
the PWRGD latch is reset and the Q2 DMOS device will shut
off (high impedance). The pin will quickly be pulled high by
the external module (or an optional pull-up resistor or
equivalent) which in turn will disable it. If a pull-up resistor is
used, it can be connected to any supply voltage that doesn’t
exceed the IC pin maximum ratings on the high end, but is
high enough to give acceptable logic levels to whatever
signal it is driving. An external clamp may be used to limit the
voltage range.
VDD
∆ V_{GATE (SECTION OF) ISL6142}
(L VERSION)
V_{GH -}
GATE
+
PWRGD
VIN+ VOUT+
ON/OFF
V_PG
+
+
-
-
V_EE
V_DH
+
+
-
-
LATCH
LOGIC
Q2
V_EE
V_EE
DRAIN
+
CL
ACTIVE LOW
ENABLE
MODULE
VIN- VOUT-
FIGURE 34. ACTIVE LOW ENABLE MODULE
The PWRGD can also drive an opto-coupler (such as a
4N25), as shown in Figure 35 or LED (Figure 36). In both
cases, they are on (active) when power is good. Resistors
R13 or R14 are chosen based on the supply voltage, and the
amount of current needed by the loads.
V_DD
(SECTION OF) ISL6142
(L VERSION)
PWRGD
LOGIC
Q2
LATCH
COMPARATORS
R13
PWRGD
OPTO
V_EE
DRAIN
FIGURE 35. ACTIVE LOW ENABLE OPTO-ISOLATOR
V_DD
(SECTION OF) ISL6142
(L VERSION)
PWRGD
R14
LOGIC
Q2
LATCH
COMPARATORS
LED (GREEN)
V_EE
DRAIN
FIGURE 36. ACTIVE LOW ENABLE LED
ISL6152 (H version; Figure 37): Under normal conditions
(DRAIN voltage - V_EE < V_PG, and ∆V_GATE - V_GATE < V_GH),
the Q3 DMOS will be on, shorting the bottom of the internal
resistor to V_EE, turning Q2 off. If the pull-up current from the
external module is high enough, the voltage drop across the
6.2kΩ resistor will look like a logic high (relative to DRAIN).
Note that the module is only referenced to DRAIN, not V_EE
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