ISL6142 Datasheet, PDF (16/23 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6142, ISL6152
C1 and R3 prevent Q1 from turning on momentarily when
power is first applied. Without them, C2 would pull the gate
of Q1 up to a voltage roughly equal to V_EE*C2/Cgs(Q1)
(where Cgs is the FET gate-source capacitance) before the
ISL6142/52 could power up and actively pull the gate low.
Place C1 in parallel with the gate capacitance of Q1; isolate
them from C2 by R3.
C1 =[(Vinmax - Vth)/Vth] * (C2+Cgd) - where Vth is the
FET’s minimum gate threshold, Vinmax is the maximum
operating input voltage, and Cgd is the FET gate-drain
capacitance.
R3 - its value is not critical, a typical value of 18kΩ is
recommended but values down to 1KΩ can be used. Lower
values of R3 will add delay to gate turn-on for hot insertion
and the single retry event following a hard fault.
R7/R8/R9 - are used to sense the load current (R7/R8) and
convert the scaled output current (IS_OUT) to a voltage (R9)
that would typically be the input signal to an A to D converter.
R7 is connected between -IS and the R1 sense resistor.
These two resistors set the I_SENSE (current through the
Rsense resistor) to IS_OUT scaling factor based on equation 5
below. R8 does not effect the scaling factor but should match
R7 to minimize IS_OUT error. Their tolerance should be +/-1%,
which will typically result in an output current error of less than
5% for a full scale condition. The trace layout is also critical to
obtain optimum performance. The traces connecting these
resistors to the device pins (IS+ and IS-) and to the R1 sense
resistor should be kept as short as possible, match in length,
and be isolated from the main current flow as illustrated in
figure 30.
R9 is used to convert the IS_OUT current to voltage and is
connected between the IS_OUT pin and -V_IN. The current
flowing through the resistor (EQ. 5) should not exceed 600µA
and the voltage on the CT pin will clamp at approximately 8V.
IS_OUT
=
I_S
E
N
S
E
×
R_{-----S----E----N----S----E--}
R7
(EQ. 5)
To select the appropriate resistor values for the application
the user must first define the R1 sense resistor value and the
maximum load current to be detected/measured. The value
of R7 should then be selected such that the maximum IS_OUT
current is in the 400-500µA range. For example, if the user
wanted to detect and measure fault currents up to the hard
fault comparator trip point (10A); the maximum IS_OUT
current using the application components in figure 23 would
be [10A x (.02/400] = 500µA. The value of R9 should be set
to accommodate the dynamic range of the A to D converter.
For this example, a 5KΩ resistor would produce a full scale
input voltage to the converter of 2.5V (500µA x 5KΩ).
Figures 32 and 33 illustrate the typical output voltage
response of the current sense circuit for the Over-Current
Time-out and hard fault single retry events.
R10 - is a pull-up resistor for the open drain FAULT output
pin which goes active low when the Over-Current latch is set
(Over-Current Time-Out). The output signal is referenced to
V_EE and the resistor is connected to a positive voltage, 5V or
less, with respect to V_EE. A typical value of 5KΩ is
recommended. A fault indicator LED can be placed in series
with the pull-up resistor if desired. The resistor value should
be selected such that it will allow enough current to drive the
LED adequately (brightness).
C3 - is the capacitor used to program the current limit time-
out period. When the Over-Current threshold is exceeded a
20µA (nominal) current source will charge the C3 capacitor
from V_EE to approximately 8.5V. When the voltage on the CT
pin exceeds the 8.5V threshold, the GATE pin will
immediately be pulled low with a 70ma pull down device, the
Over-Current latch will be set, and the FET will be turned off.
If the Over-Current condition goes away before the time-out
period expires, the CT pin will be pulled back down to V_EE,
and normal operation will resume. Note that any parasitic
capacitance from the CT pin to -V_IN will effectively add to
C3. This additional capacitance should be taken into account
when calculating the C3 value needed for the desired time-
out period.
The value of C3 can be calculated using equation 6 where dt
is the time-out period, dv is the CT pin threshold, and I_CT is
the capacitor charging current.
C3
=
-^d----^t-
dv
×
I_C
T
=
t_---i_-m_------e_----o_---u_----t
8.5 V
×
20
×10^–6
(EQ. 6
Q2- is an N-channel logic FET used to drive the disable pin
(DIS). The DIS pin is used to enable/disable the external
pass transistor (Q1) by turning the GATE drive voltage on or
off. The DIS pin can also be used to reset the Over-Current
latch by toggling the pin high and then low. When Q2 is off,
the DIS pin is pulled high with an internal 500KΩ resistor,
connected to an internal +5V (V_EE + 5V) supply rail (10µA).
In this condition the GATE pin is low, and Q1 is turned off.
When Q2 is on, the DIS pin is pulled low to V_EE allowing the
GATE pin to pull up and turn on Q1. The gate of Q2 will
typically be driven low (<1.5V) or High (>3.0V) with external
logic circuitry referenced to the negative input (-V_IN).
Low-side Application
Although this IC was designed for -48V systems, it can also
be used as a low-side switch for positive 48V systems; the
operation and components are usually similar. One possible
difference is the kind of level shifting that may be needed to
interface logic signals to the IC. For example, many of the IC
functions are referenced to the IC substrate, connected to the
V_EE pin, but this pin may be considered -48V or GND,
depending upon the polarity of the system. Also, the input or
output logic (running at 5V or 3.3V or even lower) might be
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