ISL6142 Datasheet, PDF (10/23 Pages) Intersil Corporation – Negative Voltage Hot Plug Controller

ISL6142, ISL6152
Test Circuit and Timing Diagrams (Continued)
V_EE - V_DRAIN = 0V
V_DH
DRAIN
V_DRAIN - V_EE = 8.0V
8.0V
t_PLHDH
PWRGD
1.0V
V_DH
DRAIN
V_EE - V_DRAIN = 0V
PWRGD
V_DRAIN - V_EE = 8.0V
8.0V
t_PHLDH
1.0V
V_PWRGD - V_DRAIN = 0V
FIGURE 6A. DRAIN HIGH TO PWRGD (INACTIVE) HIGH
(ISL6142)
FIGURE 6B. DRAIN HIGH TO PWRGD (INACTIVE) LOW
(ISL6152)
FIGURE 6. DRAIN TO PWRGD/PWRGD INACTIVE TIMING
3V
DIS
0V
GATE
13.6V
0V
1.50V
t_PHLDIS t_PLHDIS
1V
2.2V
1V
FIGURE 7. DISABLE TO GATE TIMING (ISL6142/52)
GATE
∆V_GATE - V_GATE = 0V
FAULT
t_PHLF
1.4V
1.0V
FIGURE 8. FAULT TO GATE TIMING (ISL6142/52)
50mV
0V
13.6V
SENSE
GATE
t_PHLSENSE
~4V (depends on FET threshold)
SENSE
0V
13.6V
GATE
210mV
t_PHLHF
V_EE
FIGURE 9. SENSE TO GATE (CURRENT LIMIT) TIMING
FIGURE 10. SENSE TO GATE (HARD FAULT) TIMING
UV
t_PHLCB
GATE
1.0V
1.0V
Over-Current Time-Out
FIGURE 11. CURRENT LIMIT TO GATE TIMING
V_SENSE
V_OUT
t_R
90%
10%
90%
t_F
10%
FIGURE 12. OUTPUT CURRENT RISE AND FALL TIME
10