ISL6595 Datasheet, PDF (18/22 Pages) Intersil Corporation – Digital Multiphase Controller

ISL6595
phase will respond. If the transient is severe, (up to three
phases) respond. This avoids a dramatic sinking or sourcing
event, which can cause oscillation. The ISL6595 controller
itself uses hysteretic control algorithms after the transient
event to ensure that the power stages return to normal
operation smoothly with minimal ringing. External-loop ATR
(overshoot only) provides an output to engage an additional
low latency low side stage capable of quickly discharging the
load. This consists of a small low-side FET with a very fast
gate driver. Internal- and external-loop ATR can be used
independently or in conjunction to optimize transient
performance.
Output Configurations
The ISL6595 provides 6 configurable outputs that are used
to drive up to 6-phase power stages. The PWM6 output may
also be configured to provide the external loop ATRL output
to drive a low side overshoot control FET.
For driving external MOSFETs, tri-valent FET drivers must
be used. The driver input circuit has two thresholds (upper
and lower) along with a bias network such that its input is
centered between the two thresholds when the ISL6595
output driver is three-stated. This allows three values to be
defined for the signal, depending whether the output is high,
low, or high impedance. If the input signal is high, the gate
driver turns the high-side switch on. If the input signal is low,
the gate driver turns the low-side switch on. If the input
signal is three-state, the driver does not turn either high-side
or low-side switches on and the power stage is high
impedance or three-stated. Intersil’s ISL6594A, ISL6594B
and ISL6596 FET drivers are optimized to operate with the
ISL6595.
The output drive signals are generated using a 3.3V
tri-valent driver. All outputs are tri-stated during reset,
configuration, and inactive state. This allows the user to set
the appropriate level to tri-state the power stage, using
external pull-up or pull-down resistors.
Output Firing Sequence
The PWM output and current sense (ISEN) pins of the
ISL6595 have been assigned such that they can be placed
sequentially for PC board layouts (i.e. phase 2 next to 1,
phase 3 next to 2, etc...). The output phases are set in a
pre-wired firing order to facilitate layout of high phase count
systems. For high phase count systems, the VRD layout in
the motherboard will likely require the power components to
be laid out across two sides of the processor. The firing
sequence shown in the table below ensures that for a highly
distributed power array, the maximum spatial distribution can
be obtained between sequential phases.
TABLE 3. OUTPUT FIRING SEQUENCE AND NUMBER OF
PHASES
#P
FIRING SEQUENCE
2 1Æ2Æ1Æ2Æ1Æ2Æ1Æ2Æ1Æ2Æ1Æ2…
3 1Æ2Æ3Æ1Æ2Æ3Æ1Æ2Æ3Æ1Æ2Æ3…
4 1Æ4Æ2Æ3Æ1Æ4Æ2Æ3Æ1Æ4Æ2Æ3…
5 1Æ4Æ2Æ5Æ3Æ1Æ4Æ2Æ5Æ3Æ1Æ4…
6 1Æ4Æ2Æ5Æ3Æ6Æ1Æ4Æ2Æ5Æ3Æ6…
Fault Detection and Fault Handling
The ISL6595 provides a very flexible fault detection reporting
and handling mechanism. Fault detection capability
includes:
• Input Undervoltage Protection (IUVP)
• Output Overvoltage Protection (OOVP)
• Output Undervoltage Protection (OUVP)
• Per Phase Overcurrent Protection (OCP)
• Total Output Overcurrent
• Two levels of Internal Temperature Protection
• Four levels of External Temperature Protection
• Configuration Failure
• Calibration Time-out Failure
All individual faults are latched and reported over the serial
interface. Two configurable fault outputs are provided
(FAULT1, FAULT2). Each output allows independent
masking of all faults, allowing a subset of faults to be
reported over that pin. The outputs can also be configured
as either latched or unlatched, active high or active low
polarity, and CMOS or open drain outputs.
Typical usage of the configurable fault pins would be as a
crowbar signal to drive an external crowbar device,
temperature alert to notify the system a thermal shutdown is
imminent, or as an interrupt to cause a micro-controller to
poll the fault registers.
Shutdown operation also allows a subset of faults to be
individually masked. Additionally, the shutdown recovery can
be either autonomous or latched. For autonomous recovery,
the faults are not latched, so if the fault condition is
eliminated when the controller returns to an inactive state, it
will wait for a programmable time period, and then attempt a
new soft-start. If the fault condition reoccurs, the controller
will recommence the shutdown sequence, continuing this
cycle indefinitely until the fault conditions is eliminated. The
programmable delay ensures a sufficiently low duty cycle to
prevent the regulator components from being damaged from
power cycling, assuming the fault condition itself is not
immediately destructive.
18
FN9192.2
December 4, 2008