ISL6316_06 Datasheet, PDF (18/29 Pages) Intersil Corporation – Enhanced 4-Phase PWM Controller with 6-Bit VID Code Capable of Precision rDS(ON) or DCR Differential Current Sensing for VR10 Application

ISL6316
Assuming the microprocessor controls the VID change at 1-bit
every T_VID, the relationship between the time constant of
R_REF and C_REF network and T_VID is given by Equation 13.
C_REF R_REF = T_VID
(EQ. 13)
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within
the proper window of operation, PGOOD asserts logic high.
ISL6316 INTERNAL CIRCUIT EXTERNAL CIRCUIT
VCC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10kΩ
EN_PWR
910Ω
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a high-
impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6316 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6316 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6316 will not inadvertently turn off unless the bias
voltage drops substantially (see Electrical
Specifications).
2. The ISL6316 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6316 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6316 becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6316 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
4. The VID code must be valid and not be OFF codes. When
controller receives VID OFF code, the controller will
execute a 2-cycle delay before changing the overvoltage
trip level to the shut-down level and disabling PWM.
Overvoltage shutdown can not be reset using this code.
When all conditions above are satisfied, ISL6316 begins the
soft-start and ramps the output voltage based on the VID code
and offset voltage.
The “OFF“ VID codes (“111111” and ‘111110’) are latched. If
ISL6316 is enabled with an “OFF“ VID code present, the
regulator will be latched off and recycling the POR, EN_VTT
or EN_PWR signal is needed to restart.
Soft-start
ISL6316 based VR has 2 periods during soft-start as shown in
Figure 11. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have a fixed delay
period TD1. After this delay period, the VR will begin the first
soft-start ramp until the output voltage reaches the final
setting.
The soft-start time is the sum of the 2 periods as shown in the
following equation.
T_SS = TD1 + TD2
(EQ. 14)
TD1 is the fixed delay with the typical value equal to 1.36ms.
During TD2, ISL6316 digitally controls the DAC voltage
change at 6.25mV per step. The time for each step is equal to
the period of the soft-start oscillator, which is defined by the
resistor Rss from SS pin to GND. The soft-start ramp time
TD2 can be calculated based on the following equation.
TD2 = ^{V-----I--D-----x---R-----S}----^S-- (μs)
6.25 x 25
(EQ. 15)
For example, when VID is set to 1.1V and the Rss is equal to
100kΩ, the soft-start ramp time TD2 will be 704µs.
18
FN9227.1
December 12, 2006