ISL6316_06 Datasheet, PDF(10/29 Page) Intersil Corporation – Enhanced 4-Phase PWM Controller with 6-Bit VID Code Capable of Precision rDS(ON) or DCR Differential Current Sensing for VR10 Application

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ISL6316_06 Datasheet, PDF (10/29 Pages) Intersil Corporation – Enhanced 4-Phase PWM Controller with 6-Bit VID Code Capable of Precision rDS(ON) or DCR Differential Current Sensing for VR10 Application

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ISL6316

Electrical Specifications Operating Conditions: VCC = 5V, Unless Otherwise Specified (Continued)

PARAMETER

TEST CONDITIONS

MIN TYP MAX UNITS

POWER GOOD AND PROTECTION MONITORS

Leakage Current of PGOOD

With externally pull-up resistor connected to VCC

Î¼A

PGOOD Low Voltage

Undervoltage Threshold

IPGOOD = 4mA

VDIFF Falling

0.3

48 50 52 %VID

PFGOOD Reset Voltage

VDIFF Rising

58 60 62 %VID

Overvoltage Protection Threshold

Before valid VID

1.250 1.275 1.300 V

After valid VID, the voltage above VID

150 175 200 mV

Overvoltage Protection Reset Threshold

0.38 0.40 0.42 V

NOTES:

3. These parts are designed and adjusted for accuracy with all errors in the voltage loop included.

4. Spec guaranteed by design.

5. During soft-start, VDAC rises from 0 to 1.1V first and then ramp to VID voltage after receiving valid VID.

6. Soft-start ramp rate is determined by the adjustable soft-start oscillator frequency at the speed of 6.25mV per cycle.

Functional Pin Description

VCC

Supplies the power necessary to operate the chip. The

controller starts to operate when the voltage on this pin

exceeds the rising POR threshold and shuts down when the

voltage on this pin drops below the falling POR threshold.

Connect this pin directly to a +5V supply.

GND

Bias and reference ground for the IC. The bottom metal base

of ISL6316 is the GND.

EN_PWR

This pin is a threshold-sensitive enable input for the controller.

Connecting the 12V supply to EN_PWR through an

appropriate resistor divider provides a means to synchronize

power-up of the controller and the MOSFET driver ICs. When

EN_PWR is driven above 0.875V, the ISL6316 is active

depending on status of EN_VTT, the internal POR, and

pending fault states. Driving EN_PWR below 0.745V will clear

all fault states and prime the ISL6316 to soft-start when re-

enabled.

EN_VTT

This pin is another threshold-sensitive enable input for the

controller. Itâs typically connected to VTT output of VTT

voltage regulator in the computer mother board. When

EN_VTT is driven above 0.875V, the ISL6316 is active

depending on status of ENLL, the internal POR, and pending

fault states. Driving EN_VTT below 0.745V will clear all fault

states and prime the ISL6316 to soft-start when re-enabled.

Use this pin to set up the desired switching frequency. A

resistor, placed from FS to ground will set the switching

frequency. The relationship between the value of the resistor

and the switching frequency will be described by approximate

equations.

Use this pin to set up the desired start-up oscillator frequency.

A resistor, placed from SS to ground will set up the soft-start

ramp rate.The relationship between the value of the resistor

and the soft-start ramp up time will be described by

approximate equation.

VID5, VID4, VID3, VID2, VID1 and VID0

These are the inputs to the internal DAC that generates the

reference voltage for output regulation. Connect these pins

either to open-drain outputs with or without external pull-up

resistors or to active-pull-up outputs. All VID pins have 40ÂµA

internal pull-up current sources that diminish to zero as the

voltage rises above the logic-high level. These inputs can be

pulled up externally as high as VCC plus 0.3V.

VDIFF, VSEN, and RGND

VSEN and RGND form the precision differential remote-sense

amplifier. This amplifier converts the differential voltage of the

remote output to a single-ended voltage referenced to local

ground. VDIFF is the amplifierâs output and the input to the

regulation and protection circuitry. Connect VSEN and RGND

to the sense pins of the remote load.

FB and COMP

Inverting input and output of the error amplifier respectively.

FB can be connected to VDIFF through a resistor. A properly

chosen resistor between VDIFF and FB can set the load line

(droop), when IDROOP pin is tied to FB pin. The droop scale

factor is set by the ratio of the ISEN resistors and the inductor

DCR or the lower MOSFET rDS(ON). COMP is tied back to FB

through an external R-C network to compensate the regulator.

FN9227.1

December 12, 2006

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