ISL62391 Datasheet, PDF (18/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers

ISL62391, ISL62392
As an example, suppose the high-side MOSFET has a total
gate charge Q_g, of 25nC at V_GS = 5V, and a ΔV_BOOT of
200mV. The calculated bootstrap capacitance is 0.125µF; for
a comfortable margin, select a capacitor that is double the
calculated capacitance. In this example, 0.22µF will suffice.
Use an X7R or X5R ceramic capacitor.
Layout Considerations
As a general rule, power should be on the bottom layer of
the PCB and weak analog or logic signals are on the top
layer of the PCB. The ground-plane layer should be adjacent
to the top layer to provide shielding. The ground plane layer
should have an island located under the IC, the
compensation components, and the FSET components. The
island should be connected to the rest of the ground plane
layer at one point.
VIAS TO
G^VR^IAO^SU^TN^OD
G_PR_LO_ANU_END
PLANE
IN^IND^DU^UC^CT^TOO^RR
H_HI_IG_GH_H-S_-SID_IDE_E
M_MO_OS_SFE_FT_ES_TS
G^GN^ND^D
VOUT
O^OU^UT^TP^PU^UT^T
C^CA^AP^PA^AC^CI^IT^TO^ORR^SS
SSCCHOOTTTTKKYY
DDIIODDEE
PHHAASSEE
NNOODDEE
LO^LOW^W-S^-SID^IDE^E
M^MO^OS^SF^FE^ET^TS^S
IN^IP^NPU^UT^T
V_VIN_IN
CA^CAP^PA^AC^CIT^ITO^OR^RS^S
FIGURE 29. TYPICAL POWER COMPONENT PLACEMENT
Because there are two SMPS outputs and only one PGND
pin, the power train of both channels should be laid out
symmetrically. The line of bilateral symmetry should be
drawn through pins 4 and 18. This layout approach ensures
that the controller does not favor one channel over another
during critical switching decisions. Figure 29 illustrates one
example of how to achieve proper bilateral symmetry.
Signal Ground and Power Ground
The bottom of the ISL62391, ISL62392 TQFN package is the
signal ground (GND) terminal for analog and logic signals of
the IC. Connect the GND pad of the ISL62391, ISL62392 to
the island of ground plane under the top layer using several
vias for a robust thermal and electrical conduction path.
Connect the input capacitors, the output capacitors, and the
source of the lower MOSFETs to the power ground plane.
PGND (Pin 19)
This is the return path for the pull-down of the LGATE
low-side MOSFET gate driver. Ideally, PGND should be
connected to the source of the low-side MOSFET with a
low-resistance, low-inductance path.
VIN (Pin 17)
The VIN pin should be connected close to the drain of the
high-side MOSFET, using a low resistance and low
inductance path.
Co
PIN 4 (VCC)
LINE OF SYMMETRY
PIN 18 (PVCC)
ISL6239
L2
L2 U2
Ci
Ci
L1 U1
PGND PLANE
PHASE PLANES
VOUT PLANES
VIN PLANE
L1
Co
FIGURE 30. SYMMETRIC LAYOUT GUIDE
VCC (Pin 4)
For best performance, place the decoupling capacitor very
close to the VCC and GND pins.
PVCC (Pin 18)
For best performance, place the decoupling capacitor very
close to the PVCC and respective PGND pin, preferably on
the same side of the PCB as the ISL62391, ISL62392 IC.
EN (Pins 11 and 24), and PGOOD (Pin 1)
These are logic signals that are referenced to the GND pin.
Treat as a typical logic signal.
OCSET (Pins 10 and 25) and ISEN (Pins 9 and 26)
For DCR current sensing, the current-sense network,
consisting of R_OCSET and C_SEN, needs to be connected to
the inductor pads for accurate measurement. Connect
R_OCSET to the phase-node side pad of the inductor, and
connect C_SEN to the output side pad of the inductor. The
ISEN resistor should also be connected to the output pad of
the inductor with a separate trace. Connect the OCSET pin
to the common node of node of R_OCSET and C_SEN.
For resistive current sensing, connect R_OCSET from the
OCSET pin to the inductor side of the resistor pad. The ISEN
resistor should be connected to the V_OUT side of the resistor
pad.
In both current-sense configurations, the resistor and
capacitor sensing elements, with the exclusion of the current
sense power resistor, should be placed near the
corresponding IC pin. The trace connections to the inductor
or sensing resistor should be treated as Kelvin connections.
FB (Pins 7 and 28), and VOUT (Pins 8 and 27)
The VOUT pin is used to generate the R³ synthetic ramp
voltage and for soft-discharge of the output voltage during
shutdown events. This signal should be routed as close to
the regulation point as possible. The input impedance of the
FB pin is high, so place the voltage programming and loop
18
FN6666.4
December 22, 2008