ISL62391 Datasheet, PDF (15/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers

ISL62391, ISL62392
needs to match the inductor time constant L/DCR. The value
of C_SEN is then written as Equation 10:
C_SEN
=
--------------------^L---------------------
R_OCSET • DCR
(EQ. 10)
For example, if L is 1.5µH, DCR is 4.5mΩ, and R_OCSET is
9kΩ, the choice of C_SEN = 1.5µH/(9kΩ x 4.5mΩ) = 0.037µF.
Upon converter start-up, the C_SEN capacitor bias is 0V. To
prevent false OCP during this time, a 10µA current source
flows out of the OUT1 pin, generating a voltage drop on the
R_O resistor, which should be chosen to have the same
resistance as R_OCSET. When the PGOOD pin goes high, the
OUT1 pin current source will be removed.
When an OCP fault is declared, the PGOOD pin will pull-down
to 32Ω and latch-off the converter. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage, or until V_IN has decayed below the falling
POR threshold.
When using a discrete current sense resistor, inductor
time-constant matching is not required. Equation 7 remains
unchanged, but Equation 8 is modified in Equation 11:
V_OCSET1–V_OUT1 = I_L • R_SENSE – 10μA • R_OCSET
(EQ. 11)
Furthermore, Equation 9 is changed in Equation 12:
R_OCSET
=
I_{--O-----C-----}•_--R_{-----S----E----N----S----E--}
10 μ A
(EQ. 12)
Where R_SENSE is the series power resistor for sensing
inductor current. For example, with an R_SENSE = 1mΩ and
an OCP target of 10A, R_OCSET = 1kΩ.
Overvoltage Protection
The OVP fault detection circuit triggers after the FB pin
voltage is above the rising overvoltage threshold for more
than 2µs. The FB pin voltage is 0.6V in normal operation.
The rising overvoltage threshold is typically 116% of that
value, or 1.16*0.6V = 0.696V.
For both the ISL62391 and ISL62392, when an OVP fault is
declared, the PGOOD pin will pull-down with 32Ω and latch-off
the converter. The OVP fault will remain latched until the EN
pin has been pulled below the falling EN threshold voltage, or
until V_IN has decayed below the falling POR threshold. During
the latch condition, the ISL62391 will tri-state the PHASE
node by turning both UGATE and LGATE off until the latch is
cleared.
Although latched, the ISL62392 LGATE gate-driver output will
retain the ability to toggle the low-side MOSFET on and off in
response to the output voltage transversing the OVP rising
and falling thresholds. The LGATE gate-driver will turn on the
low-side MOSFET to discharge the output voltage, thus
protecting the load from potentially damaging voltage levels.
The LGATE gate-driver will turn off the low-side MOSFET
once the FB pin voltage is lower than the falling overvoltage
threshold for more than 2µs. The falling overvoltage threshold
is typically 106% of the reference voltage, or 1.06*0.6V =
0.636V. This soft-crowbar process repeats as long as the
output voltage fault is present, allowing the ISL62392 to
protect against persistent overvoltage conditions.
Undervoltage Protection
The UVP fault detection circuit triggers after the FB pin
voltage is below the undervoltage threshold for more than
2µs. The undervoltage threshold is typically 86% of the
reference voltage, or 0.86*0.6V = 0.516V. If a UVP fault is
declared, the PGOOD pin will pull-down with 32Ω and latch-off
the converter. The fault will remain latched until the EN pin
has been pulled below the falling enable threshold, or if V_IN
has decayed below the falling POR threshold.
Programming the Output Voltage
When the converter is in regulation, there will be 0.6V
between the FB and GND pins. Connect a two-resistor
voltage divider across the OUT and GND pins with the
output node connected to the FB pin, as shown in Figure 27.
Scale the voltage-divider network such that the FB pin is
0.6V with respect to the GND pin when the converter is
regulating at the desired output voltage. The output voltage
can be programmed from 0.6V to 5.5V.
Programming the output voltage is written as Equation 13:
V_OUT
=
V_REF
•
⎛
⎜1
⎝
+
R^-----_B^--R--_O^---T-_T^--O--_T^---P-_O^----_M^---_{⎠⎟⎞}
(EQ. 13)
Where:
- V_OUT is the desired output voltage of the converter
- The voltage to which the converter regulates the FB pin
is the V_REF (0.6V)
- R_TOP is the voltage-programming resistor that connects
from the FB pin to the converter output. In addition to
setting the output voltage, this resistor is part of the loop
compensation network
- R_BOTTOM is the voltage-programming resistor that
connects from the FB pin to the GND pin
Choose R_TOP first when compensating the control loop, and
then calculate R_BOTTOM according to Equation 14:
R_BOTTOM
=
--^V----^R----^E----^F----^•---^R----^T----^O----^P----
V_OUT – V_REF
(EQ. 14)
Compensation Design
Figure 27 shows the recommended Type-II compensation
circuit. The FB pin is the inverting input of the error amplifier.
The COMP signal, the output of the error amplifier, is inside the
chip and unavailable to users. C_INT is a 100pF capacitor
integrated inside the IC that connects across the FB pin and the
COMP signal. R_TOP, R_FB, C_FB and C_INT form the Type-II
compensator. The frequency domain transfer function is given
by Equation 15:
G_COMP(s)
=
-----------¹-----+-----^s----^•--⁽---^R----^T----^O-----^P-----+----^R-----^F----^B----⁾--^•---^C-----^F---^B-------------
s
•
R_TOP
•
C_INT
•
(
1
+
s
•
R_FB
•
C)
FB
(EQ. 15)
15
FN6666.4
December 22, 2008