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ISL62391 Datasheet, PDF (12/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers
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ISL62391, ISL62392
Theory of Operation
Three Output Controller
The ISL62391, ISL62392 generates three regulated output
voltages. Two are produced with switch-mode power supplies
(SMPS), and the third by a low dropout linear regulator (LDO).
An additional 5V LDO (PVCC) is used to power the chip
during operation, allowing the ISL62391, ISL62392 to regulate
all outputs from a single power source (VIN) with no need for
a separate quiescent supply. This makes the ISL62391,
ISL62392 an ideal choice as system regulator for notebook
PCs. Because the two SMPS channels are identical and
almost entirely independent, all conclusions drawn apply to
both channels unless otherwise noted.
Modulator and Switching Frequency
The ISL62391, ISL62392 modulator features Intersil’s R3
technology, a hybrid of fixed frequency PWM and variable
frequency hysteretic control. Intersil’s R3 technology can
simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The R3 modulator synthesizes an AC signal, VR,
which is an analog representation of the output inductor
ripple current. The duty-cycle of VR is the result of charge
and discharge current through a ripple capacitor, CR. The
current through CR is provided by a transconductance
amplifier that measures the VIN and VO pin voltages. The
positive slope of VR can be written as Equation 1:
VRPOS = gm ⋅ (VIN – VOUT)
(EQ. 1)
The negative slope of VR can be written as Equation 2:
VRNEG = gm ⋅ VOUT
(EQ. 2)
Where gm is the gain of the transconductance amplifier.
RIPPLE CAPACITOR VOLTAGE CR
WINDOW VOLTAGE VW
(WRT VCOMP)
ERROR AMPLIFIER
VOLTAGE VCOMP
PWM
FIGURE 23. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor, RW, connected across the FSET and
GND pins. The VR, VCOMP, and VW signals feed into a
window comparator in which VCOMP is the lower threshold
voltage and VW is the higher threshold voltage. Figure 23
shows PWM pulses being generated as VR traverses the
VW and VCOMP thresholds. The PWM switching frequency
is proportional to the slew rates of the positive and negative
slopes of VR; it is inversely proportional to the voltage
between VW and VCOMP. Equation 3 illustrates how to
calculate the window size based on output voltage and
frequency set resistor.
VW = gm ⋅ VOUT ⋅ (1 – D) ⋅ RW
(EQ. 3)
The frequency can be expressed in Equation 4:
FSW
=
--------1---------
K ⋅ RW
(EQ. 4)
Inverting Equation 4 allows easy selection of RW for a
desired FSW:
RW = -K-----⋅---F1----S----W---
(EQ. 5)
For Equations 3 through 5:
gm = 1.66µs
K = 1.7 x 10-10 (±20%)
D = VOUT/VIN
Power-On Reset
The ISL62391, ISL62392 is disabled until the voltage at the
VIN pin has increased above the rising power-on reset
(POR) threshold. Conversely, the controller will be disabled
when the voltage at the VIN pin decreases below the falling
POR threshold.
In addition to VIN POR, the PVCC pin is also monitored. If its
voltage falls below 4.2V, the SMPS outputs will be shut
down. This ensures that there is sufficient BOOT voltage to
enhance the upper MOSFET.
EN, Soft-Start and PGOOD
The ISL62391, ISL62392 uses a digital soft-start circuit to
ramp the output voltage of each SMPS to the programmed
regulation setpoint at a predictable slew rate. The slew rate
of the soft-start sequence has been selected to limit the
in-rush current through the output capacitors as they charge
to the desired regulation voltage. When the EN pins are pulled
above their rising thresholds, the PGOOD Soft-Start Delay,
tSS, starts and the output voltage begins to rise. The FB pin
ramps to 0.6V in approximately 1.5ms and the PGOOD pin
goes to high impedance approximately 1.25ms after the FB
pin voltage reaches 0.6V.
12
FN6666.4
December 22, 2008
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