ISL62391 Datasheet, PDF (16/20 Pages) Intersil Corporation – High-Efficiency, Triple-Output System Power Supply Controller for Notebook Computers

ISL62391, ISL62392
C_INT = 100pF
R_FB
C_FB
R_TOP
-
VO
FB
COMP
EA
+
R_BOTTOM
REF
ISL62391, ISL62392
FIGURE 27. COMPENSATION REFERENCE CIRCUIT
The LC output filter has a double pole at its resonant frequency
that causes rapid phase change. The R³ modulator used in the
ISL62391, ISL62392 makes the LC output filter resemble a first
order system in which the closed loop stability can be achieved
with the recommended Type-II compensation network. Intersil
provides a PC-based tool (example page is shown later) that
can be used to calculate compensation network component
values and help simulate the loop frequency response.
3.3V Linear Regulator
In addition to the two SMPS outputs, the ISL62391, ISL62392
also provides a fixed 3.3V LDO output (LDO3) capable of
sourcing 100mA continuous current. LDO3 draws its power
from PVCC and can be independently enabled from both
SMPS channels.
LDO3 also has a current limit feature with a nominal level of
180mA. Currents in excess of the limit will cause the LDO3
voltage to drop dramatically, limiting the power dissipation.
Thermal Monitor and Protection
LDO3 and PVCC LDOs can dissipate non-trivial power inside
the ISL62391, ISL62392 at high input-to-output voltage ratios
and full load conditions. To protect the silicon, ISL62391,
ISL62392 continually monitors the die temperature. If the
temperature exceeds +150°C, all outputs will be turned off to
sharply curtail power dissipation. The outputs will remain off
until the junction temperature has fallen below +135°C.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 16:
D
=
-^V-----^O---
V_IN
(EQ. 16)
The output inductor peak-to-peak ripple current is written as
Equation 17:
I_PP
=
V_-----O-----•_--(_---1_{-----–----}D_-----)
f_SW • L
(EQ. 17)
A typical step-down DC/DC converter will have an I_P-P of
20% to 40% of the maximum DC output load current. The
value of I_P-P is selected based upon several criteria, such as
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated by Equation 18:
P_COPPER = I_LOAD2 • DCR
(EQ. 18)
Where I_LOAD is the converter output DC current.
The copper loss can be significant so attention has to be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components, as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_P-P can flow. Current I_P-P develops a
corresponding ripple voltage V_P-P across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as Equation 19:
ΔV_ESR = I_P-P • ESR
(EQ. 19)
and Equation 20:
ΔV_C
=
----------^I--^P----^---^P-----------
8 • C_O • f_SW
(EQ. 20)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V_P-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Low
inductance capacitors should be considered in this scenario.
A capacitor dissipates heat as a function of RMS current and
frequency. Be sure that I_P-P is shared by a sufficient quantity
of paralleled capacitors so that they operate below the
maximum rated RMS current at f_SW. Take into account that
the rated value of a capacitor can fade as much as 50% as
the DC voltage across it increases.
16
FN6666.4
December 22, 2008