ISL26712_14 Datasheet, PDF (18/21 Pages) Intersil Corporation – 12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs

ISL26712, ISL26710, ISL26708
fundamental. Also referred to as Spurious Free Dynamic Range
(SFDR). Normally, the value of this specification is determined by
the largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it will be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and fb,
any active device with nonlinearities will create distortion products
at sum and difference frequencies of mfa ± nfb where m and n =
0, 1, 2 or 3. Intermodulation distortion terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb), and (fa –2fb).
The ISL26712/10/08 is tested using the CCIF standard, where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second order terms are usually
distanced in frequency from the original sine waves, while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification, where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dBs.
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 3dB for a full-scale input.
Common-Mode Rejection Ratio (CMRR)
The common-mode rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power of
a 250mV_P-P sine wave applied to the common-mode voltage of
AIN+ and AIN– of frequency fs shown in Equation 3:
CMRR(dB) = 10log(Pfl ⁄ Pfs)
(EQ. 3)
Pfl is the power at frequency f in the ADC output; Pfs is the power
at frequency fs in the ADC output.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Zero-Code Error
This is the deviation of the midscale code transition (111...111 to
000...000) from the ideal AIN+ – AIN– (i.e., 0 LSB).
Positive Gain Error
This is the deviation of the last code transition (011...110 to
011...111) from the ideal AIN+ – AIN– (i.e., +REF – 1 LSB), after
the zero code error has been adjusted out.
Negative Gain Error
This is the deviation of the first code transition (100...000 to
100...001) from the ideal AIN+ – AIN– (i.e., – REF + 1 LSB), after
the zero code error has been adjusted out.
Track and Hold Acquisition Time
The track and hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track mode
for its output to reach and settle to within 0.5 LSB of the applied
input signal.
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to ADC VDD
supply of frequency f_S. The frequency of this input varies from
1kHz to 1MHz as shown by Equation 4.
PSRR(dB) = 10log (Pf ⁄ Pfs)
(EQ. 4)
Pf is the power at frequency f in the ADC output; Pfs is the power
at frequency f_s in the ADC output.
Application Hints
Grounding and Layout
The printed circuit board that houses the ISL26712/10/08
should be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes
since it gives the best shielding. Digital and analog ground planes
should be joined in only one place, and the connection should be
a star ground point established as close to the GND pin on the
ISL26712/10/08 as possible. Avoid running digital lines under
the device, as this will couple noise onto the die. The analog
ground plane should be allowed to run under the
ISL26712/10/08 to avoid noise coupling.
The power supply lines to the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other sections of the
board, and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed-through the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should be
decoupled with μF tantalum capacitors in parallel with 0.1μF
capacitors to GND. To achieve the best from these decoupling
components, they must be placed as close as possible to the device.
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FN7999.3
September 5, 2012