English
Language : 

ISL26712_14 Datasheet, PDF (15/21 Pages) Intersil Corporation – 12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs
ISL26712, ISL26710, ISL26708
5V
0.1µF
+ BULK
1 DNC DNC 8
2 VIN
DNC 7
2.5V
3 COMP VOUT 6
4 GND TRIM 5
ISL21090
ISL267440 VDD
ISL267450AVREF
0.1µF
0.1µF
FIGURE 30. PRECISION VOLTAGE REFERENCE FOR +5V SUPPLY
+2.7V TO +3.6V
OR +5V
+
BULK
VIN 1
VOUT 2
GND
3
ISL21010
0.1µF
1.25, 2.048 OR 2.5V
VDD
ISL267817
VREF
0.1µF
0.1µF
FIGURE 31. VOLTAGE REFERENCE FOR +2.7V TO +3.6V, OR FOR +5V SUPPLY
Converter Operation
The ISL26712, ISL26710 and ISL26708 are designed to
minimize power consumption by only powering up the SAR
comparator during conversion time. When the converter is in
track mode (its sample capacitors are tracking the input signal)
the SAR comparator is powered down. The state of the converter
is dictated by the logic state of CS. When CS is high the SAR
comparator is powered down while the sampling capacitor array
is tracking the input. When CS transitions low, the capacitor array
immediately captures the analog signal that is being tracked.
After CS is taken low, the SCLK pin is toggled 16 times. For the
first 3 clocks, the comparator is powered up and auto-zeroed,
then the SAR decision process is begun. This process uses 12
SCLK cycles for the 12-bit ISL26712. Each SAR decision is
presented to the SDATA output on the next clock cycle after the
SAR decision is performed. The SAR process (12 bits) is
completed on SCLK cycle 15. At this point in time, the SAR
comparator is powered down and the capacitor array is placed
back into Track mode. The last SAR comparator decision is
output from SDATA on the 16th SCLK cycle. When the last data
bit is output from SDATA the output switches to a logic 0 until CS
is taken high, at which time, the SDATA output enters a High-Z
state.
The ISL26710 and ISL26708 will take fewer clock cycles for their
SAR decisions and will output fewer data bits. The extra bits
following the output of the LSB will be logic zeroes.
Figures 32, 33, and 34 illustrate the system timing for the 12-,
10- and 8-bit converters respectively.
15
FN7999.3
September 5, 2012