ISL26712_14 Datasheet, PDF (13/21 Pages) Intersil Corporation – 12-Bit, 10-Bit and 8-Bit, 1MSPS SAR ADCs

ISL26712, ISL26710, ISL26708
Functional Description
The ISL26712/10/08 are based on a successive approximation
register (SAR) architecture utilizing capacitive charge
redistribution digital-to-analog converters (DACs). Figure 24
shows a simplified representation of the converter. During the
acquisition phase (ACQ), the differential input is stored on the
sampling capacitors (CS). The comparator is in a balanced state
since the switch across its inputs is closed. The signal is fully
acquired after t_ACQ has elapsed and the switches then transition
to the conversion phase (CONV) so the stored voltage may be
converted to digital format. The comparator will become
unbalanced when the differential switch opens and the input
switches transition (assuming that the stored voltage is not
exactly at mid-scale). The comparator output reflects whether the
stored voltage is above or below mid-scale, which sets the value
of the MSB. The SAR logic then forces the capacitive DACs to
adjust up or down by one quarter of full-scale by switching in
binarily weighted capacitors. Again, the comparator output
reflects whether the stored voltage is above or below the new
value, setting the value of the next lowest bit. This process
repeats until all 12 bits have been resolved.
011...111
011...110
1LSB = 2•VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF
+ ½LSB
0V
+VREF
– 1½LSB
ANALOG INPUT
AIN+ – (AIN–)
+VREF
– 1LSB
FIGURE 25. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL26712/10/08 feature a fully differential input with a
nominal full-scale range equal to twice the applied VREF voltage.
Each input swings VREF V_P-P, 180° out-of-phase from one
another for a total differential input of 2*VREF (refer to
Figure 26).
AIN+
AIN–
CONV C_S
ACQ
ACQ
ACQ CONV
CONV CS
VREF
SAR
LOGIC
FIGURE 24. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the SCLK pin to generate a
conversion result. The allowable frequency range for SCLK is
10kHz to 18MHz (556SPS to 1MSPS). Serial output data is
transmitted on the falling edge of SCLK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of SCLK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the
VREF pin to set the full-scale input range and common-mode
voltage. See “Voltage Reference Input” on page 14 for more
details.
ADC Transfer Function
The output coding for the ISL26712/10/08 is twos complement.
The first code transition occurs at successive LSB values (i.e.,
1 LSB, 2 LSB, and so on). The LSB size of the ISL26712 is
2*VREF/4096, while the LSB size of the ISL26710 is
2*VREF/1024 and the ISL26708 is 2*VREF/512. The ideal
transfer characteristic of the ISL26712/10/08 is shown in
Figure 25.
V_REF(P-P)
AIN+
V_CM
V_REF(P-P)
AIN–
FIGURE 26. DIFFERENTIAL INPUT SIGNALING
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
Figure 27 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the AIN+ and AIN– pins within
specification. Figures 28 and 29 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the AIN+ and
AIN– pins within the supply rails. Additional restrictions are
imposed due to the required headroom of the input circuitry,
resulting in practical limits shown by the shaded area.
13
FN7999.3
September 5, 2012