ISL1539A_14 Datasheet, PDF (18/23 Pages) Intersil Corporation – Dual Port VDSL2 Line Driver

ISL1539A
external 2.88kΩ resistor will double the current while
leaving the I_ADJ pin voltage at approximately -0.4V,
which is well within rated minimum. This approach
should be used with great caution as very high internal
power dissipations can easily be produced. However, it
can be a useful approach to extend operation,
particularly when operating on lower total supply
voltages than the rated typical of ±12V.
+V_{CC IBIAS IBIAS} +V_CC
+3.3V
+3.3V
+VCC _{IBIAS IBIAS} +V_CC
+3.3V
+3.3V
50k
50k 50k
50k
COAB
+1V
+1.4V
C1AB
COCD
+1.4
V
C1CD
RO 500
I_ADJ
FIGURE 46. BIAS CONTROL CIRCUIT
The current in RO divides in 1/4 levels to form the bias
current for the 4 pairs of differential switches. Each pair
of switches controls the quiescent current for one port.
For instance, C0_AB and C1_AB control the quiescent
current for the port constructed from amplifiers A and B.
If both control lines are unconnected externally, the
internal 50kΩ pull-up will switch the differential pairs to
divert the 100µA tail currents into the supply turning off
the amplifiers. Taking both control pins low will pass both
I_BIAS lines on into scaling current sources. With I_REF
grounded, this will give the typical 27.2mA total
quiescent current for a port shown in the “Electrical
Specification” tables on page 5. Taking C₀ high (>2V)
while leaving C₁ low (<0.8V) will reduce the current into
a port to a typical 23mA. Taking C₁ high, while leaving C₀
low will reduce the current in a port to a typical 13.5mA
supply current. Table 2 summarizes the operation modes
for ISL1539A for each port.
TABLE 2. POWER MODES OF THE ISL1539A
C₁
C₀
OPERATION
0
0
I_S Full Power Mode
0
1
I_S Medium Power Mode
1
0
I_S Low Power Mode
1
1
Power-Down
Performance Considerations
Driving Capacitive Loads
All closed loop op amps are susceptible to reduced phase
margin when driving capacitive loads. This shows up as
peaking in the frequency response that can, in extreme
situations, lead to oscillations. The ISL1539A is designed
to operate successfully with small capacitive loads such
as layout parasitics. As the parasitic capacitance
increases, it is best consider a small resistor in series
with the output to isolate the phase margin effects of the
capacitor. Figure 20 on page 10 shows the effect of
capacitive load on the differential gain of 10 circuit. With
15pF on each output, we see about 5dB peaking. This will
increase quickly at higher C_loads. If this degree of
peaking is unacceptable, a small series resistor can be
used to improve the flatness as shown in Figure 21.
Output DC Error Model
Often, non-inverting bias current (ibn), inverting bias
current (ibi), and input offset voltage (Vio) are quite low
for typical op amps.
Vio, ibn, ibi can be mapped to output offset both
common and differential mode. Consider the circuit in
Figure 47.
+Vcc
± Vio
+
±ibn
Rb
-
Rf
Vcm
Rcm
±ibi
Zg
±ibi
+Vcc _Rf
-
Rb
Vcm ± Vocm ± Vodm
±Vio
+
± ibn
FIGURE 47. DC ERROR MODEL
The output common mode offset voltage (Vo-cm) is
derived from the input common mode voltage (Vi-cm),
as expressed in Equations 8 and 9:
Vicm = ±2 × ibn × Rcm ± ibn × Rb ± Vio
(EQ. 8)
Vocm = ± Vicm ± Rf × ibi
(EQ. 9)
The output differential mode offset voltage (Vo-dm) is
derived from the input differential mode voltage (Vi-dm),
as expressed in Equations 10 and 11:
Vidm = ±Δibn × Rb ± ΔVio
(EQ. 10)
Vodm = ±Vidm × _⎝⎛1 + ²--_R--^R--_g---^f_⎠⎞ ± Δibi × Rf
(EQ. 11)
Example:
Referring to the “Electrical Specification” tables on
page 6:
ibn = 8µA, Δibn = 2µA
ibi = 75µA, Δibi = 35µA
Vio = 8mV, ΔVio = 2mV
18
FN6916.0
September 23, 2009