ISL1539A_14 Datasheet, PDF (17/23 Pages) Intersil Corporation – Dual Port VDSL2 Line Driver

ISL1539A
V_o
V_i
=
A_oc
R_L
R_L + Z_o
(EQ. 2)
The goal of the positive feedback resistor, R_P, is to
provide some “gain” in the apparent output impedance
over just the 2*R_M. It also will act to increase the A_OC
over the simple differential gain equation if a synthesis
factor (SF) is defined as shown in Equation 3:
SF
=
1−
1
R_f −
R_m
R_p
(EQ. 3)
We can see this "gain" is achieved by letting R_P be > R_F
The closer R_P is to R_F-R_M, the more "gain" is achieved
but at the risk of instability. With this SF defined as
shown above, the exact A_OC and Z_O will be as shown in
Equations 4 and 5:
A_oc
= SF (1+ 2 ^Rf
R_g
+
R _f − R_{m )}
R_p
(EQ. 4)
Z_o = SF (2R_m )
(EQ. 5)
For test purposes, the circuit shown in Figure 45 was
configured to achieve the following results.
SF = 2.19
A_OC = 17.7V/V
Z_O = 66Ω
Putting these together into the gain to an 82.6Ω load
gives the following test condition as shown by
Equation 6.
V_o
V_i
=
A_oc
R_L
R_L + Z_o
= 17.7 ^82.6Ω
82.6Ω + 66Ω
= 9.84_⎜⎛ ^V
⎝^V
⎟⎞
⎠
(EQ. 6)
The advantage offered by this technique is that for
whatever swing we desire at the load, there is less rise
through the physical output matching resistor than if we
simply inserted two 33Ω R_M resistors to achieve the 66Ω
output impedance achieved in this test circuit. Whatever
load current is required in R_L will rise to the output pins
through 2*R_M. The rise from the load swing to the output
pin swing is given by Equation 7:
R_L + 2R_m
R_L
(EQ. 7)
This was only 1.36 for the test circuit shown above. In
differential circuits the ±V_P at the output pins produces a
4V_P for the differential peak-to-peak voltage. Hence a
±10V swing at each output in the above circuit will
produce a 40V_P-P differential swing which will drop to the
load divided by 1.36 - or a 29.41V_P-P differential swing.
Distortion and MTPR
The ISL1539A is intended to provide very low distortion
levels under the demanding conditions required by the
discrete multi-tone (DMT) characteristic of modern DSL
modulations. The standard test for linearity is the Multi-
Tone Power Ratio (MTPR) test where a specified standard
is loaded up with discrete carriers over the specified
frequencies in such a way as to produce the maximum
rated line power and Peak to Average Ratio (PAR) with
some tones missing. The measure of linearity is the
separation from the active tones vs. a missing tone. To
the extent that the amplifier is slightly non-linear, it will
fold a small amount of power into the missing tones
through intermodulation products for the active tones.
Figure 17 shows the circuit operating at the low power
setting used to test ADSL2+ frequency plan and power.
For this test the carriers are spaced at 5kHz.
This -60dBc MTPR is exceptional for the very low 13.5mA
total quiescent current used in this configuration.
Operating at reduced power targets on the line will
improve MTPR as will operating the amplifiers at higher
quiescent current.
The characteristic curves show the exceptional single
tone performance available using the ISL1539A. At the
highest quiescent power, operating at a simple
differential gain of 10V/V, Figure 22 shows the 5V_P-P
distortion plot.
Figure 22 shows a better than -80dBc through 8MHz for
the 2nd and 3rd harmonics. The rapid rise in the spurious
above 10MHz is coming from the onset of fine scale slew
limiting effects. By 20MHz, the output signal is requiring
a differential slew rate of 300V/µs - a significant portion
of the available 3000V/µs slew rate available at full
power.
Power Control Function
Figure 46 shows a simplified schematic for the power
control features included in the ISL1539A. Each of the 4
differential pairs shown in the drawing are used to steer
control currents (I_BIAS terms) into additional current
mirrors (not shown) that control the quiescent bias
current for each of the two ports. This bias control shares
the I_ADJ pin. When I_ADJ is grounded, the typical supply
current levels shown in the “Electrical Specifications”
tables on page 5 are produced. Inserting an external
resistor to ground in the I_ADJ pin will scale the quiescent
currents down, as shown in Figure 38.
It is also possible to scale the I_ADJ currents up by tying
the I_ADJ pin through a resistor to a negative supply. As
long as the resulting voltage divider between this
external negative voltage and the internal +0.4V on the
other side of the 500Ω resistor stays above the
maximum rated negative voltage on the I_ADJ pin (-1V).
For instance, to double the typical quiescent current
levels, the current in the I_ADJ pin must be doubled from
its nominal 800µA level. Using a -5V supply through an
17
FN6916.0
September 23, 2009