HFA3783 Datasheet, PDF (18/34 Pages) Intersil Corporation – I/Q Modulator/Demodulator and Synthesizer

HFA3783
most often used VCO’s in the market have positive KVCO’s
where the VCO frequency increases with an increase in
control voltage. In this case, the charge pump current shall
“source” current (to the main capacitor of the loop filter)
when the VCO frequency becomes less than the desired
frequency of operation. The phase comparison and charge
pump output behavior in a open loop system is illustrated in
Figure 5. The comparator’s inputs (the top two waveforms of
Figure 5 are from the N and R counters. The output from the
“N” counter and the prescaler, labelled as “VCO/[P*B+A]”
shows a lower frequency than the output from the “R”
counter labeled “REF/R”. REF/R is usually called “reference”
frequency. The bottom waveform represents the charge
pump sourcing current as it has been programmed. Because
it is an open loop system, the charge pump current pulse
width will increase and follow the phase comparator’s output.
The charge pump signal can be developed across a resistor
connected between pin 22 and a power supply of half the
V_CC voltage. In the case where the VCO/[P*B+A] frequency
is higher than the REF/R frequency, the bottom waveform
would have negative pulse width variations indicating the
Charge Pump sinking current.
The closed loop concept can be understood intuitively by
observing the bottom waveform and noticing the tendency of
the Charge Pump to “charge” a capacitor (loop filter) and
increase the VCO voltage control accordingly. As the
VCO/[P*B+A] frequency becomes higher than the REF/R
frequency, the Charge Pump begins to sink current and the
VCO control voltage begins to drop. The process would
continue in equilibrium with expected sharp reverting polarity
pulses at the REF/R reference frequency. Figure 6 depicts a
simple Charge Pump polarity concept and includes the
output of the Lock Detect Pin of the HFA3783. This pin has
other applications and will be covered in the next section.
PLL Synthesizer and DC Offset Clock
Programming
A three wire CMOS Serial interface (CLK, DATA, LE)
programs various counters and operational modes of the
HFA3783 PLL. It also programs the DC offset adjust counter
and operation of the LPF section. Figure 1 in the
Specification section shows the Timing Diagram for this
interface.
Short clock periods in the order of 20ns can be used to
program this interface. The serial data is clocked on the
rising edge of the serial clock into a serial 20-bit shift register
with the MSB first. See the PLL synthesizer and DC Clock
Programming Table for details. The serial register is always
active when the LE pin is held low. On the rising edge of the
LE pin, the serial register is loaded and latched into the
addressed registers for the particular function. The two least
significant bits address the intended register for loading the
serial data. This interface has been designed for a minimum
LE pulse width. There is no need to discontinue the clock
during loading of the 4 intended registers.
NOTE: Upon a rising edge on LE, the HFA3783 PLL unlocks
the loop during a random period varying from 0 to
1/(reference frequency). Fast frequency hopping
applications may be affected during this time.
÷N
REF
CP
LD
FIGURE 6. SIMPLIFIED CP AND LOCK DETECT OUTPUT WAVEFORMS
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