HFA3783 Datasheet, PDF (14/34 Pages) Intersil Corporation – I/Q Modulator/Demodulator and Synthesizer

HFA3783
Overall Device Description
The HFA3783 is a highly integrated baseband converter for
half duplex wireless data applications. It features all the
necessary blocks for baseband modulation and
demodulation of “I” and “Q” quadrature multiplexing signals
including an on chip three wire interface PLL stage used with
an external VCO for Local Oscillator applications. Device RF
properties have been optimized through the thoughtful
consideration of layout, device pinout, and a completely
differential design. These RF properties include immunity
from common mode signals such as noise and crosstalk,
optimized dynamic range for low power requirements and
reduced relevant parasitics and settling times. The single
power supply requirements from 2.7V_DC to 3.3V_DC makes
the HFA3783 a good choice for portable transceiver designs.
Receive Chain
The HFA3783 has two cascaded very low distortion
integrated AGC IF amplifiers with frequency response from
70 to 600MHz. These differential amplifiers exhibit better
than 70dB of both voltage gain and AGC range. Noise figure,
output compression and intercept point variations with the
AGC range have been tailored to achieve cascaded
performances as presented in the AC Electrical
Specifications. To increase the receiver’s overall AGC
dynamic range and conserve compression specifications, a
Peak Detector has been added in parallel with the AGC’s
input. The Peak Detector is used to control an external step
attenuator or the RF gain of the front end LNA stage.
Following the AGC stages, an AC coupled down conversion
pair of quadrature doubly balanced mixers are used for “I”
and “Q” baseband IF processing. These differential
converters are driven by an internal differential quadrature
generator with broadband response and excellent
quadrature properties. For broadband operation, the Local
Oscillator frequency input is twice the desired frequency of
demodulation. Duty cycle and signal purity requirements for
the 2XLO input using this type of quadrature architecture are
less restrictive for the HFA3783. Ground reference or
differential input signals from -15dBm to 0dBm and
frequencies up to 1200MHz (2XLO) can be used.
The output of the “I” and “Q” mixers are DC coupled to a pair
of multistage differential 2nd pole antialiasing baseband
filters with DC offset correction. The DC offset correction is
enabled with an external control pin allowing for correction to
occur during transmit, receive or power down modes. The
baseband filter’s cut off frequency of 7.7MHz is optimized for
11M chips/s spread spectrum applications. The baseband
outputs are differential, with common mode DC voltage
outputs tracking an internal band gap voltage reference. The
Band Gap reference is also available to the user by an
external pin. The “I” and “Q” baseband voltages can swing
up to 1Vpp differential, following the AC Electrical
Specifications across the AGC range. Figure 16 illustrates
the cascaded gain characteristics versus AGC voltage
control for the HFA3783 receive section.
Transmit Chain
The HFA3783 modulator section has a frequency response
of 70 to 600MHz. It consists of differential “I” and “Q”
baseband inputs requiring pre-shaped analog data levels up
to 500mVpp. A common mode voltage of around 1.3V is
required for proper operation of the four differential input
pins. There are no internal pre-shaping filters in the
modulator section. Following the differential input stages, a
DC coupled up conversion pair of quadrature doubly
balanced mixers are used for “I” and “Q” baseband IF
processing. These differential mixers are driven by the same
internal LO quadrature generator used in the receive
section. Their phase and gain characteristics, including I/Q
matching, are well suitable for accurate data transmission.
The final stage is an AGC amplifier with 70dB of dynamic
range. Please refer to Figure 35.
Detailed Description
Receive AGC/ Peak Detector
The receive AGC amplifier section consists of 4 stages and
each stage is built out of four parallel, distributed
gain/degeneration differential pairs. In half duplex packet
transmission linear systems, the receive AGC control’s
thermal and supply voltage variations over the packet
duration are more important than gain control linearity.
Therefore, the chosen architecture addresses very
constricted temperature, voltage and process variations. The
control is based on a band gap voltage reference “gm”
distribution scheme. In addition, the design provides fast
AGC settling times as well as fast turn on/off characteristics
for packetized information. The four stage AGC amplifier has
a typical maximum voltage gain of 44dB and exhibits better
than 70dB of dynamic range, providing an attenuation in
excess of 26dB at minimum gain. The design can be used
differential or single ended, exhibiting the same gain
characteristics: however, consideration is necessary due to
common mode spurious signals. One of the main features of
this front end is the high impedance and small variation of S
parameters when the HFA3783 is switched between transmit
and receive modes. This feature permits the use of a
combination match network and the use of a single SAW
filter for both halves of the duplex operation. S parameters
for the differential and single ended applications are
available in the S Parameter Tables of this document. The
matching network arrangements will be discussed later in IF
Interface section.
A Peak Detector is placed in parallel with the input of the first
stage of the AGC amplifier. It consists of a high frequency
differential full wave rectifier and a voltage to current
converter. The Peak Detector has limited range and is used
to trip a comparator in an external baseband processor
when the voltage swing at the input of the AGC amplifier is
about 150mVpp. Once the external comparator is tripped, its
logic output level steps the LNA’s gain down keeping the RF
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