HFA3783 Datasheet, PDF (10/34 Pages) Intersil Corporation – I/Q Modulator/Demodulator and Synthesizer

HFA3783
Phase Lock Loop Electrical Specifications
PARAMETER
Operating 2X LO Frequency
Reference Oscillator Frequency
Selectable Prescaler Ratios (2 Settings)
Swallow Counter Divide Ratio (A Counter)
Programmable Counter Divide Ratio
(B Counter)
Reference Counter Divide Ratio (R Counter)
Reference Oscillator Sensitivity
Reference Oscillator Duty Cycle
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Current/Tolerance
Charge Pump Sink/Source Mismatch
Charge Pump Output Compliance
Charge Pump High Z leakage
Charge Pump Supply Voltage
Serial Interface Clock Width
Serial Interface Data/Clk Set-Up Time
Serial Interface Data/Clk Hold Time
Serial Interface Clk/LE Set-Up Time
Serial Interface LE Pulse Width
TEST CONDITIONS
Test Diagram
Test Diagram
Single or Differential Sine
Inputs
CMOS Single or
Complementary
CMOS Inputs
250µA Selection +/- 25%
500µA Selection +/- 25%
750µA Selection +/- 25%
1mA Selection +/- 25%
High Z state
High Level
Low level
TEMP.
(^oC)
MIN
TYP
MAX
UNITS
Full
140
-
1200
MHz
Full
-
-
50
MHz
Full
16/17
N/A
32/33
-
Full
0
-
127
-
Full
3
-
2047
-
Full
3
Full
0.5
-
32767
-
-
-
V_PP
Full
-
CMOS
-
-
Full
40
-
60
%
Full
0.18
0.25
0.32
mA
Full
0.375
0.5
0.625
mA
Full
0.56
0.75
0.94
mA
Full
0.75
1.0
1.25
mA
Full
-
-
15
%
Full
0.5
-
CPV_DD-0.5
V
Full
-10
±0.1
10
µA
Full
2.7
-
3.6
V
Full
20
-
-
ns
Full
20
-
-
ns
Full
20
-
-
ns
Full
10
-
-
ns
Full
20
-
-
ns
Full
20
-
-
ns
POWER ENABLE TRUTH TABLE
PLL_PE
PE1
PE2
(SERIAL BUS)
STATUS
0
0
1
Power Down State, PLL Registers in Save Mode, Inactive PLL, Active Serial Interface
1
1
1
Receive State, Active PLL
1
0
1
Transmit State, Active PLL
0
1
1
Inactive Transmit and Receive States, Active PLL, Active Serial Interface
X
X
0
Inactive PLL, Disabled PLL Registers, Active Serial Interface
PLL Synthesizer and DC Offset Clock Programming Table
REGISTER
DEFINITION
SERIAL
BITS LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R Counter
0
0 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) X (Don’t Care)
A/B Counter 0
1 A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10)
10