ISL78010 Datasheet, PDF (17/18 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
Over-Temperature Protection
An internal temperature sensor continuously monitors the
die temperature. In the event that the die temperature
exceeds the thermal trip point of +140°C, the device will shut
down.
Layout Recommendation
Device performance including efficiency, output noise,
transient response and control loop stability is dramatically
affected by the PCB layout. PCB layout is critical, especially
at high switching frequency.
There are some general guidelines for layout:
1. Place the external power components (the input
capacitors, output capacitors, boost inductor and output
diodes, etc.) in close proximity to the device. Traces to
these components should be kept as short and wide as
possible to minimize parasitic inductance and resistance.
2. Place V_REF and V_DD bypass capacitors close to the pins.
3. Minimize the length of traces carrying fast signals and
high current.
Typical Application Diagram
4. All feedback networks should sense the output voltage
directly from the point of load, and be as far away from LX
node as possible.
5. The power ground (PGND) and signal ground (SGND)
pins should be connected at only one point near the main
decoupling capacitors.
6. A signal ground plane, separate from the power ground
plane, should be used for ground return connections for
feedback resistor networks (R₁, R₁₁, R₄₁) and the V_REF
capacitor, C₂₂, the C_DELAY capacitor C₇ and the
integrator capacitor C₂₃.
7. Minimize feedback input track lengths to avoid switching
noise pick-up.
8. Connect all "NC" pins to the ground plane to improve the
thermal performance and switching noise immunity
between pins.
A demo board is available to illustrate the proper layout
implementation.
Q₁
NODE 1
V_IN
C₀
C₁
1nF 10µF
x2
C₁₀
4.7µF
C₇
0.22µF
R₆ 10Ω
C₆ 4.7µF
R₇ 10kΩ
NODE 1
C₄₁ 0.1µF ^VREF
R₄₃
500Ω
C₂₂
0.1µF
*
Q₅
V_LOGIC
(2.5V) _C31
4.7µF
*
R₄₂
5.4kΩ ^R41
5kΩ
L₁
6.8µH
PG
CDELAY
LX
FBB
LX
D₁
46.5kΩ R₂
R₁
5kΩ
C₂-C₃ R₉
10µF _1MΩ
X2
R₇ OPEN
C₇ OPEN
Q₄
C₁₆
22nF
C₉
0.1µF
R₈
10kΩ
A_VDD
(12V)
VDD
EN
VREF
DRVL
FBL
SGND
DELB
CINT ^{R10 C23}
10kΩ _CP
4.7nF
1nF
R₁₃
LX
C₁₃
0.1µF
DRVP
FBP
7kΩ
C₁₄
Q₃
0.1µF D₁₂
R₁₂ 230kΩ
R₁₁
C₁₅
20kΩ
0.47µF
C₁₂
0.1µF
C₂₄
*
R₂₃
0.1µF
DRVN
FBN
PGND
3kΩ
R₂₂ 104k
R₂₁
20k
V_REF
C₂₅
Q₂
0.1µF D₂₁
C₂₀
4.7µF
*
C₁₁
0.1µF
D₁₁
V_ON
(15V)
LX
*
V_OFF
(-5V)
NOTE: SGND should be connected to PGND at one point only.
17
FN6501.0
May 30, 2007