ISL78010 Datasheet, PDF (12/18 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
Operation of the DELB Output Function
An open drain DELB output is provided to allow the boost
output voltage, developed at C₂ (See “Typical Application
Diagram” on page 17), to be delayed via an external switch
(Q₄) to a time after the V_BOOST supply and negative V_OFF
charge pump supply have achieved regulation during the
start-up sequence shown in Figures 14 and 16. This then
allows the A_VDD and V_ON supplies to start-up from 0V
instead of the normal offset voltage of V_IN-V_DIODE (D₁) if Q₄
were not present.
When DELB is activated by the start-up sequencer, it sinks
50µA allowing a controlled turn-on of Q₄ and charge-up of
C₉. C₁₆ can be used to control the turn-on time of Q₄ to
reduce inrush current into C₉. The potential divider formed
by R₉ and R₈ can be used to limit the V_GS voltage of Q₄ if
required by the voltage rating of this device. When the
voltage at DELB falls to less than 0.6V, the sink current is
increased to ~1.2mA to firmly pull DELB to 0V.
The voltage at DELB is monitored by the fault protection
circuit so that if the initial 50µA sink current fails to pull DELB
below ~0.6V after the start-up sequencing has completed,
then a fault condition will be detected and a fault time-out
ramp will be initiated on the C_DEL capacitor (C₇).
Operation of the PG Output Function
The PG output consists of an internal pull-up PMOS device to
V_IN, to turn-off the external Q₁ protection switch and a current
limited pull-down NMOS device which sinks ~15µA allowing a
controlled turn-on of Q₁ gate capacitance. C_O is used to
control how fast Q₁ turns-on - limiting inrush current into C₁.
When the voltage at the PG pin falls to less than 0.6V, the PG
sink current is increased to ~1.2mA to firmly pull the pin to 0V.
The voltage at PG is monitored by the fault protection circuit
so that if the initial 15µA sink current fails to pull PG below
~0.6V after the start-up sequencing has completed, then a
fault condition will be detected and a fault time-out ramp will
be initiated on the C_DEL capacitor (C₇).
Cascaded MOSFET Application
A 20V N-Channel MOSFET is integrated in the boost
regulator. For the applications where the output voltage is
greater than 20V, an external cascaded MOSFET is needed
as shown in Figure 22. The voltage rating of the external
MOSFET should be greater than V_BOOST.
V_IN
LX
FB
ISL78010
V_BOOST
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH
OUTPUT VOLTAGE APPLICATIONS
Linear-Regulator Controllers (V_ON, V_LOGIC, and
V_OFF)
The ISL78010 includes three independent linear-regulator
controllers, in which two are positive output voltage (V_ON
and V_LOGIC), and one is negative. The V_ON, V_OFF, and
V_LOGIC linear-regulator controller functional diagrams,
applications circuits are shown in Figures 23, 24, and 25
respectively.
Calculation of the Linear Regulator Base-Emitter
Resistors (R_BL, R_BP and R_BN)
For the pass transistor of the linear regulator, low frequency
gain (h_FE) and unity gain frequency (f_T) are usually specified
in the datasheet. The pass transistor adds a pole to the loop
transfer function at f_p = f_T/h_FE. Therefore, in order to
maintain phase margin at low frequency, the best choice for
a pass device is often a high frequency low gain switching
transistor. Further improvement can be obtained by adding a
base-emitter resistor R_BE (R_BP, R_BL, R_BN in the Functional
Block Diagrams on page 13), which increase the pole
frequency to: f_p = f_T*(1+ h_FE *re/R_BE)/h_FE, where
re = KT/qIc. So choose the lowest value R_BE in the design
as long as there is still enough base current (I_B) to support
the maximum output current (I_C).
We will take as an example the V_LOGIC linear regulator. If a
Fairchild FMMT549 PNP transistor is used as the external
pass transistor (Q₅ in the application diagram) then for a
maximum V_LOGIC operating requirement of 500mA, the data
sheet indicates h_FE(min) = 100.
The base-emitter saturation voltage is: Vbe_max = 1.25V
(note this is normally a Vbe ~ 0.7V, however, for the Q₅
transistor an internal Darlington arrangement is used to
increase it's current gain, giving a 'base-emitter' voltage of
2 x V_BE).
(Note that using a high current Darlington PNP transistor for
Q₅ requires that V_IN > V_LOGIC + 2V. Should a lower input
voltage be required, then an ordinary high gain PNP
transistor should be selected for Q₅ so as to allow a lower
collector-emitter saturation voltage).
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FN6501.0
May 30, 2007