ISL78010 Datasheet, PDF (15/18 Pages) Intersil Corporation – Automotive Grade TFT-LCD Power Supply

ISL78010
Equation 17 gives the boundary between discontinuous and
continuous boost operation. For continuous operation (LX
switching every clock cycle) we require that:
I_{--A----V----D----D-----}(_--l_--o_----a_----d_---)_---->_-----D_-----×_-----(_---1_{----–-----}D_-----)_---×_-----V_----I--N--
2 × L × f_OSC
(EQ. 17)
where the duty cycle, D = (A_VDD - V_IN)/A_VDD
For example, with V_IN = 5V, f_OSC = 1.0MHz and A_VDD = 12V
we find continuous operation of the boost converter can be
guaranteed for:
L = 10μH and I_AVDD > 61mA
(EQ. 18)
L = 6.8μH and I_AVDD > 89mA
(EQ. 19)
L = 3.3μH and I_AVDD > 184mA
(EQ. 20)
Charge Pump Output Capacitors
Ceramic capacitors with low ESR are recommended. With
ceramic capacitors, the output ripple voltage is dominated by
the capacitance value. The capacitance value can be
chosen by Equation 21:
C_O
U
T
≥
---------------------^I--^O----^U-----^T----------------------
2 × V_RIPPLE × f_OSC
(EQ. 21)
where f_OSC is the switching frequency.
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For
a successful power up, there should be six peaks at V_CDLY.
When a fault is detected, the device will latch off until either
EN is toggled or the input supply is recycled.
When the input voltage is higher than 2.5V, an internal
current source starts to charge C_CDLY to an upper threshold
using a fast ramp followed by a slow ramp. During the initial
slow ramp, the device checks whether there is a fault
condition. If no fault is found, C_CDLY is discharged after the
first peak and V_REF turns on.
During the second ramp, the device checks the status of
V_REF and over-temperature. At the peak of the second
ramp, PG output goes low and enables the input protection
PMOS Q₁. Q₁ is a controlled FET used to prevent in-rush
current into V_BOOST before V_BOOST is enabled internally.
Its rate of turn on is controlled by C_o. When a fault is
detected, M1 will turn off and disconnect the inductor from
V_IN.
With the input protection FET on, NODE1 (See “Typical
Application Diagram” on page 17) will rise to ~V_IN. Initially
the boost is not enabled so V_BOOST rises to V_IN-V_DIODE
through the output diode. Hence, there is a step at V_BOOST
during this part of the start-up sequence. If this step is not
desirable, an external P-MOSFET can be used to delay the
output until the boost is enabled internally. The delayed
output appears at A_VDD.
V_BOOST soft-starts at the beginning of the third ramp. The
soft-start ramp depends on the value of the C_DLY capacitor.
For C_DLY of 220nF, the soft-start time is ~2ms.
V_REF and V_LOGIC turn on when input voltage (V_DD)
exceeds 2.5V. When a fault is detected, the outputs and the
input protection will turn off but V_REF will stay on.
V_OFF turns on at the start of the fourth peak. At the fifth
peak, the open drain o/p DELB goes low to turn on the
external PMOS Q₄ to generate a delayed V_BOOST output.
V_ON is enabled at the beginning of the sixth ramp. A_VDD,
PG, V_OFF, DELB and V_ON are checked at end of this ramp.
Fault Protection
Once the start-up sequence is complete, the voltage on the
C_DLY capacitor remains at 1.15V until either a fault is
detected or the EN pin is disabled. If a fault is detected, the
voltage on C_DLY rises to 2.4V at which point the chip is
disabled until the power is recycled or enable is toggled.
Component Selection for Start-Up Sequencing and
Fault Protection
The C_REF capacitor is typically set at 220nF and is required
to stabilize the V_REF output. The range of C_REF is from
22nF to 1µF and should not be more than five times the
capacitor on C_DEL to ensure correct start-up operation.
The C_DEL capacitor is typically 220nF and has a usable
range from 47nF minimum to several microfarads - only
limited by the leakage in the capacitor reaching µA levels.
C_DEL should be at least 1/5 of the value of C_REF (See
above). Note that with 220nF on C_DEL the fault time-out will
be typically 50ms and the use of a larger/smaller value will
vary this time proportionally (e.g. 1µF will give a fault time-
out period of typically 230ms).
Fault Sequencing
The ISL78010 has advanced fault detection systems which
protects the IC from both adjacent pin shorts during
operation and shorts on the output supplies.
A high quality layout/design of the PCB, in respect of
grounding quality and decoupling is necessary to avoid
falsely triggering the fault detection scheme - especially
during start-up. The user is directed to the “Layout
Recommendation” on page 17 and “Component Selection
for Start-Up Sequencing and Fault Protection” on page 15 to
avoid problems during initial evaluation and prototype PCB
generation.
15
FN6501.0
May 30, 2007