ISL6315 Datasheet, PDF (17/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
is important to have a symmetrical layout, preferably with the
controller equidistantly located from the two power trains it
controls. Equally important are the gate drive lines (UGATE,
LGATE, PHASE): since they drive the power train MOSFETs
using short, high current pulses, it is important to size them
accordingly and reduce their overall impedance. Equidistant
placement of the controller to the two power trains also helps
keeping these traces equally long (equal impedances,
resulting in similar driving of both sets of MOSFETs).
The power components should be placed first. Locate the
input capacitors close to the power switches. Minimize the
length of the connections between the input capacitors, C_IN,
and the power switches. Locate the output inductors and
output capacitors between the MOSFETs and the load.
Locate the high-frequency decoupling capacitors (ceramic)
as close as practicable to the decoupling target, making use
of the shortest connection paths to any internal planes, such
as vias to GND immediately next, or even onto the capacitor
solder pad.
The critical small components include the bypass capacitors
for VCC and PVCC. Locate the bypass capacitors, C_BP,
close to the device. It is especially important to locate the
components associated with the feedback circuit close to
their respective controller pins, since they belong to a high-
impedance circuit loop, sensitive to EMI pick-up. It is
important to place the R_ISEN resistor close to the respective
terminal of the ISL6315.
A multi-layer printed circuit board is recommended. Figure 10
shows the connections of the critical components for one
output channel of the converter. Note that capacitors C_xxIN
and C_xxOUT could each represent numerous physical
capacitors. Dedicate one solid layer, usually the one
underneath the component side of the board, for a ground
+12V_IN
+5V_IN
(C_F1)
DACSEL/VID12
VID4
VID3
VID2
VID1
VID0
VRM10
R_ISEN
ISEN
R’_OFS
R_OFS
SSEND
ENLL
OFS
VCC
L_IN
(C_F2)
(C_HFIN1)
C_BIN1
PVCC
BOOT1
UGATE1
C_BOOT1
Q1
PHASE1
L_OUT1
ISL6315
LGATE1
BOOT2
UGATE2
Q2
C_BOOT2
Q3
C_BIN2
(C_HFIN2)
C_BOUT
V_OUT
(C_HFOUT)
COMP
C₂
C₁
R₂
FB
R₁
PHASE2
LGATE2
PGND
GND
L_OUT2
Q4
LOCATE NEAR LOAD;
(MINIMIZE CONNECTION PATH)
LOCATE NEAR SWITCHING TRANSISTORS;
(MINIMIZE CONNECTION PATH)
LOCATE CLOSE TO IC
(MINIMIZE CONNECTION PATH)
KEY
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
17
FN9222.0
February 10, 2006