ISL6315 Datasheet, PDF (12/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
In VRM10 setting, the ISL6315 checks for a change in the
VID code six times each switching cycle. If a new code is
established and it stays the same for 3 consecutive
readings, the ISL6315 recognizes the change and
increments the reference. Specific to VRM10, the processor
controls the VID transitions and is responsible for
incrementing or decrementing one VID step at a time. In
VRM10 setting, the ISL6315 will immediately change the
reference to the new requested value as soon as the request
is validated; in cases where the reference step is too large,
the sudden change can trigger overcurrent or overvoltage
events.
In non-VRM10 settings, due to the way the ISL6315
recognizes VID code changes, up to one full switching
period may pass before a VID change registers. Thus, the
total time required for a VID change, t_DVID, is dependent on
the switching frequency (f_S), the size of the change (∆V_ID),
and the time required to register the VID change. The
approximate time required for a ISL6315-based converter in
VRM9 configuration running at typical f_S (222kHz) to
perform a 1.5V to 1.7V reference voltage change is about
196µs, as calculated using the following equation (this
example is also illustrated in Figure 5).
t_DVID
≅
--¹--
f_S


-⁴---^∆----^V----^V----^I--^D--
0.025
+ 13_
OVERVOLTAGE PROTECTION
The ISL6315 benefits from a multi-tiered approach to
overvoltage protection.
A pre-POR mechanism is at work while the chip does not
have sufficient bias voltage to initiate an active response to
an OV situation. Thus, while VCC is below its POR level, the
lower drives are three-stated and internal 5kΩ (typically)
resistors are connected from PHASE to their respective
LGATE pins. As a result, output voltage, duplicated at the
PHASE nodes via the output inductors, is effectively
clamped at the lower MOSFETs’ threshold level. This
approach ensures no catastrophic output voltage can be
developed at the output of an ISL6315-based regulator (for
most typical applications).
The pre-POR mechanism is removed once the bias is above
the POR level, and a fixed-threshold OVP goes into effect.
Based on the specific chip configuration, the OVP goes into
effect once the voltage sensed at the FB pin exceeds about
1.65V (Hammer/VR10) or 1.95V (VR9 configuration). Should
the output voltage exceed these thresholds, the lower
MOSFETs are turned on.
During soft-start, the OVP threshold changes to the higher of
the fixed threshold (1.65V/1.95V) or the DAC setting plus
200mV. At the end of the soft-start, the OVP threshold
changes to the DAC setting plus 200mV.
In any of the described post-POR functionality, OVP results
in the turn-on of the lower MOSFETs. Once turned on, the
lower MOSFETs are only turned off when the output voltage
drops below the OV comparator’s hysteretic threshold. The
OVP process repeats if the voltage rises back above the
designated threshold. The occurrence of an OVP event does
not latch the controller; should the phenomenon be
transitory, the controller resumes normal operation following
such an event.
ON/OFF CONTROL
The internal power-on reset circuit (POR) prevents the
ISL6315 from starting before the bias voltage at VCC and
PVCC reach the rising POR thresholds, as defined in
Electrical Specifications. The POR levels are sufficiently high
to guarantee that all parts of the ISL6315 can perform their
functions properly once bias is applied to the part. While bias
is below the rising POR thresholds, the controlled MOSFETs
are kept in an off state.
ISL6315
EXTERNAL CIRCUIT
+5V
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
VCC _15kΩ
ENLL
1kΩ
0.61V
OFF
ON
FIGURE 6. START-UP COORDINATION USING THRESHOLD-
SENSITIVE ENABLE (ENLL) PIN
A secondary disablement feature is available via the
threshold-sensitive enable input (ENLL). This optional
feature prevents the ISL6315 from operating until a certain
other voltage rail is available and above some selectable
threshold. For example, when down-converting off a 12V
input, it may be desirable the ISL6315-based converter does
not start up until the power input is sufficiently high. The
schematic in Figure 6 demonstrates coordination of the
ISL6315 with such a rail; the resistor components are
chosen to enable the ISL6315 as the 12V input exceeds
approximately 9.75V. Additionally, an open-drain or open-
collector device can be used to wire-AND a second (or
multiple) control signal, as shown in Figure 6. To defeat the
threshold-sensitive enable, connect ENLL to VCC directly or
via a pull-up resistor.
The ‘11111’ VID code is reserved as a signal to the controller
that no load is present. The controller is disabled while
receiving this VID code and will subsequently start up upon
receiving any other code.
12
FN9222.0
February 10, 2006