ISL6315 Datasheet, PDF (13/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
In summary, for the ISL6315 to operate, the following
conditions need be met: VCC and PVCC must be greater
than their respective POR thresholds, the voltage at ENLL
must be greater than 0.61V, and VID has to be different than
‘11111’. Once all these conditions are met, the controller
immediately initiates a soft start sequence.
SOFT-START
The soft-start function allows the converter to bring up the
output voltage in a controlled fashion, resulting in a linear
ramp-up. Following a delay of 16 PHASE clock cycles (about
70µs) between enabling the chip and the start of the ramp,
the output voltage progresses at a fixed rate of 12.5mV per
16 PHASE clock cycles.
Thus, the soft-start period (not including the 70µs wait) up to
a given voltage, V_DAC, can be approximated by the following
equation
T_SS
=
V_{-----D----A----C-----}⋅_---1_---2_----8_---0_--
f_S
where V_DAC is the DAC-set VID voltage, and f_S is the
switching frequency (typically 222kHz).
The ISL6315 also has the ability to start up into a pre-charged
output, without causing any unnecessary disturbance. The FB
pin is monitored during soft-start, and should it be higher than
the equivalent internal ramping reference voltage, the output
drives hold both MOSFETs off. Once the internal ramping
reference exceeds the FB pin potential, the output drives are
enabled, allowing the output to ramp from the pre-charged
level to the final level dictated by the DAC setting. Should the
output be pre-charged to a level exceeding the DAC setting,
the output drives are enabled at the end of the soft-start
period, leading to an abrupt correction in the output voltage
down to the DAC-set level.
FREQUENCY COMPENSATION
The ISL6315 multiphase converter behaves in a similar
manner to a voltage-mode controller. This section highlights
the design consideration for a voltage-mode controller requiring
external compensation. To address a broad range of
applications, a type-3 feedback network is recommended.
C2
COMP
R2 _C1
-
FB
E/A ⁺
VREF
R3 ^C3
R1
OSCILLATOR
PWM
CIRCUIT
V_OSC
HALF-BRIDGE
DRIVE
V_IN
L
UGATE
PHASE
LGATE
V_OUT
D
C
E
ISL6315 EXTERNAL CIRCUIT
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
OUTPUT PRECHARGED
ABOVE DAC LEVEL
OUTPUT PRECHARGED
BELOW DAC LEVEL
GND>
V_OUT (0.5V/DIV)
GND>
ENLL (5V/DIV)
T1 T2
T3
FIGURE 7. SOFT-START WAVEFORMS FOR ISL6315-BASED
MULTIPHASE CONVERTER
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable, with a small
number of adjustments, to the multiphase ISL6315 circuit. The
output voltage (V_OUT) is regulated to the reference voltage,
VREF, level. The error amplifier output (COMP pin voltage) is
compared with the oscillator (OSC) modified saw-tooth wave to
provide a pulse-width modulated wave with an amplitude of V_IN
at the PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor E.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a DC
gain, given by d_MAXV_IN/V_OSC, and shaped by the output
filter, with a double pole break frequency at F_LC and a zero at
F_CE. For the purpose of this analysis, L and D represent the
individual channel inductance and its DCR divided by 2
(equivalent parallel value of the two output inductors), while C
13
FN9222.0
February 10, 2006