ISL6315 Datasheet, PDF (14/20 Pages) Intersil Corporation – Two-Phase Multiphase Buck PWM Controller with Integrated MOSFET Drivers

ISL6315
and E represents the total output capacitance and its
equivalent series resistance.
F_LC=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE=
-----------¹------------
2π ⋅ C ⋅ E
The compensation network consists of the error amplifier
(internal to the ISL6315) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F_0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 8. Use the following guidelines for locating the
poles and zeros of the compensation network:
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F₀).
R2 = ---^V----^O-----^S----^C-----^â‹---^R-----¹-----^â‹---^F----⁰----
d_MAX ⋅ V_IN ⋅ F_LC
2. Calculate C1 such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost).
C1 = -----------------------¹------------------------
2π ⋅ R2 ⋅ 0.5 ⋅ F_LC
3. Calculate C2 such that F_P1 is placed at F_CE.
C2 = -₂---_π-----_â‹---_R-----₂-----_â‹---_CC-----₁₁----_â‹---_F----_C----_E-----–-----₁--
4. Calculate R3 such that F_Z2 is placed at F_LC. Calculate C3
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the per-channel switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in
frequency helps reduce the gain of the compensation
network at high frequency, in turn reducing the HF ripple
component at the COMP pin and minimizing resultant
duty cycle jitter.
R3 = --------^R----¹---------
F_{----S----W---- – 1}
F_LC
C3 = ------------------------¹-------------------------
2π ⋅ R3 ⋅ 0.7 ⋅ F_SW
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N-- ⋅ --------------------------¹-----+-----^s----⁽--^f--⁾----^â‹---^E-----^â‹---^C-----------------------------
V_{OSC 1 + s(f) ⋅ (E + D) ⋅ C + s}2_{(f) ⋅ L ⋅ C}
G_FB(f) = _s----₍-¹-_f--₎--+--_â‹---_Rs----⁽-₁-^f--⁾--_â‹--^â‹-₍--^RC----²-₁----^â‹-+--^C---_C--¹--₂-----₎ ⋅
⋅ -------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R-----³----⁾---^â‹---^C-----³--------------------------------
(1
+
s(f
)
⋅
R3
⋅
C3)
⋅


1
+
s
(
f
)
⋅
R
2
⋅


C^-C----1^{-1----+-⋅---C-}C^----2-2^{--}


G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
---------------¹----------------
2π ⋅ R2 ⋅ C1
F_P1
=
----------------------¹------------------------
2π ⋅ R2 ⋅ _C-^C----₁-¹----+-^â‹---^C-_C----²-₂--
F_Z2 = -₂---_π-----_â‹---₍---_R----₁-----+-¹----_R-----₃----₎---_â‹---_C-----₃--
F_P2
=
---------------¹----------------
2π ⋅ R3 ⋅ C3
Figure 9 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the
log-log graph of Figure 9 by adding the modulator gain, G_MOD
(in dB), to the feedback compensation gain, G_FB (in dB). This
is equivalent to multiplying the modulator transfer function and
the compensation transfer function and then plotting the
resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log


RR-----21--_
0
20log -^d----^M-----^A-----^X-----^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 9. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
14
FN9222.0
February 10, 2006