ISL6217 Datasheet, PDF (17/19 Pages) Intersil Corporation – Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV™ and IMVP-IV+

ISL6217
for the converter and find the intersection of this value and
the active channel curve. The worst case duty cycle is
defined as the maximum operating CORE output voltage
divided by the minimum operating battery voltage. Find the
corresponding y-axis value, which is the current multiplier.
Multiply the total full load output current, not the channel
value, by the current multiplier value found, and the result is
the RMS input current which must be supported by the input
capacitors.
FIGURE 13. INPUT RMS RIPPLE CURRENT MULTIPLIER
MOSFET Selection and Considerations
For the Intel IMVP-IV™ and IMVP-IV+™ application, which
requires up to 25 amps of current, it is suggested that 2
channel operation with (3) MOSFETs per channel be
implemented. This configuration would be: (1) High
Switching Frequency, Low Gate Charge MOSFET for the
Upper, and (2) Low rDSON MOSFETs for the Lowers.
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the
dominant design factors. The power dissipation includes
two loss components: conduction loss and switching loss.
These losses are distributed between the upper and lower
MOSFETs according to duty cycle of the converter. Refer
to the PUPPER and PLOWER equations below. The
conduction losses are the main component of power
dissipation for the lower MOSFETs. Only the upper
MOSFETs have significant switching losses, since the
lower devices turn on and off into near zero voltage. The
following equations assume linear voltage-current
transitions and do not model power loss due to the reverse-
recovery of the lower MOSFETs body diode. The gate-
charge losses are dissipated in the ISL6217 drivers and do
not heat the MOSFETs; however, large gate-charge
increases the switching time tSW, which increases the
upper MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature,
at high ambient temperature, by calculating the
temperature rise according to package thermal-resistance
specifications.
P_LOWER
=
I_O2
× r_DS(ON) × (V_IN
V_IN
−
V_OUT )
(EQ. 10)
P_UPPER
=
I_O2 × r_DS(ON) ×
V_IN
V_OUT
+
I_O
×
V_IN × t_SW
2
× F_SW
(EQ. 11)
17