ISL6217 Datasheet, PDF (15/19 Pages) Intersil Corporation – Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV™ and IMVP-IV+

ISL6217
Control Loops
The “Block Diagram” and Figure 9 shows a simplified
diagram of the voltage regulation and current control loops
for a two-phase converter. Both voltage and current
feedback are used to precisely regulate voltage and tightly
control output currents, IL1 and IL2, of the two power
channels. The voltage loop is comprised of the Error
Amplifier, Comparators, Internal Gate Drivers, and
MOSFETs. The Error Amplifier drives the modulator to force
the FB pin to the IMVP-IV™ and IMVP-IV+™ reference
minus “Droop”.
Voltage Loop
The output CORE voltage feedback is applied to the Error
Amplifier through the compensation network. The signal
seen on the FB pin will drive the Error Amplifier output either
high or low, depending on the CORE voltage. A CORE
voltage level that is lower than the IMVP-IV™ and
IMVP-IV+™ reference, as output from the 6 bit DAC, makes
the amplifier output move towards a higher output voltage
level. The amplifier output voltage is applied to the positive
inputs of the comparators by the BALANCE summing
networks. Out-of-phase sawtooth signals are applied to the
two comparators’ inverting inputs. Increasing Error Amplifier
voltage results in increased Comparator output duty cycle.
This increased duty cycle signal is passed through the PWM
circuit to the internal gate-drive circuitry. The output of the
internal gate-drive is directly connected to the gate of the
MOSFETs. Increased duty cycle or ON-time for the high side
MOSFET transistors results in increased output voltage,
VCORE, to compensate for the low output voltage sensed.
Current Loop
The current control loop keeps the channel currents in
balance. During the PWM off-time of each channel, the
voltage VrDS(ON), developed across the lower MOSFET is
sampled. Internally, the ISEN pin is held at virtual ground
during this interval, and VrDS(ON) is impressed across the
RISEN resistor. This provides current feedback proportional
to the output current of each channel. The scaled output
currents from all active channels are combined to create an
average current reference IAVERAGE, proportional to the
converter total output current. This signal is then subtracted
from the individual channel scaled output currents to
produce a current correction signal for each channel. The
current correction signal keeps each channel output current
contribution balanced relative to the other active channels.
Each current correction signal is subtracted from the error
amplifier output and fed to the individual channel PWM
circuits. For example, assume the voltage sampled across
Q4 in Figure 9 is higher than that sampled across Q2. The
ISEN2 current would be higher than ISEN1. When the two
reference currents are averaged, they accurately represent
the total output current of the converter. The reference
current IAVERAGE is then subtracted from the ISEN
currents. This results in a positive offset for Channel 2 and a
negative offset for Channel 1. These offsets are subtracted
from the error amplifier signal and perform phase balance
correction. The VERROR2 signal is reduced, while
VERROR1 would be increased. The PWM circuit would then
reduce the pulse width to lower the output current
contribution by Channel 2, while doing the opposite to
Channel 1, thereby balancing channel currents.
Droop Compensation
Microprocessors and other peripherals tend to change their
load current demands from near no-load to full load often
during operation. These same devices require minimal
output voltage deviation during a load step.
A high di/dt load step will cause an output voltage spike.
The amplitude of the spike is dictated by the output
capacitor ESR, multiplied by the load step magnitude, plus
the output capacitor ESL, times the load step di/dt. A
positive load step produces a negative output voltage spike
and vice versa. A large number of low-series-impedance
capacitors are often used to prevent the output voltage
deviation from exceeding the tolerance of some devices.
One widely accepted solution to this problem is output
voltage “Droop”, or active voltage positioning.
As shown in Figure 3 and Figure 9, the average channel
current is used to control the “Droop” current source,
IDROOP. The “Droop” current source is a controlled current
source and is proportional to output current. This current
source is approximately 87% of the averaged ISEN
currents. The Droop current is sourced out of the SOFT pin
through the Droop resistor and returns through the EA+ pin.
This creates a “Droop” voltage VDROOP, which subtracts
from the IMVP-IV™ and IMVP-IV+™ reference voltage on
SOFT to generate the voltage setpoint for the CORE
regulator.
Full load current for the Intel IMVP-IV™ and IMVP-IV+™
specification is 25 amps. ISEN currents are designed to be
32µA for this load. Knowing that the Droop Current,
sourced out of the SOFT pin, will be 87% of the ISEN
averaged currents, a “Droop” resistor RDROOP, can be
selected to provide the amount of voltage “Droop” required
at full load. The selection of this resistor is explained in the
following section.
A choice of RISEN and rDS(ON) giving a sense current
value other than 32µA at full load, will require proportional
adjustments in RDROOP and ROCSET. This may happen,
as the PTC is not found in every possible resistance value.
Selection of RDROOP
Figure 11 shows a static “Droop” load line for the 1.484V
Active Mode. The ISL6217, as previously mentioned,
allows the programming of the load line slope by the
selection of the RDROOP resistor.
V _OUT,HI
V_OUT,NOM
V_OUT,LO
(0A,1.506V)
(0A,1.484V)
(0A,1.462V)
(25A,1.431V)
(25A,1.409V)
(25A,1.387V)
-3 m_
load line
I_OUT,NL
I_OUT,MID
I_OUT,MAX
STATIC TOLERANCE BANDS
NOMINAL "DROOP" LOAD LINE
FIGURE 11. IMVP-IV™ AND IMVP-IV+™ ACTIVE MODE
STATIC LOAD LINE
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