ISL6217 Datasheet, PDF(14/19 Page) Intersil Corporation – Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV™ and IMVP-IV+

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ISL6217 Datasheet, PDF (14/19 Pages) Intersil Corporation – Precision Multi-Phase Buck PWM Precision Multi-Phase Buck PWM Positioning IMVP-IV™ and IMVP-IV+

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ISL6217

PGOOD

As previously described, the ISL6217 PGOOD pin operates

as both an input and an output. During start-up, the PGOOD

pin operates as an input (Refer to Figure 10).

RST#

IPGT

CLR

START

~ 100ns

ISL6217

3.3V

START

1.2K

PGOOD

10K

3.3V

10K

ISL6227

PGOOD

V ccp

PGOOD

Vcc_mch

3ms-12ms

CPU-UP# =

UV# and OV#

CLK_ENABLE#

IMVP4_PWRGD

FIGURE 10. INTERNAL PGOOD CIRCUITRY FOR THE ISL6217

CORE VOLTAGE REGULATOR

As per the IMVP-IVâ¢ and IMVP-IV+â¢ specification, once

the ISL6217 CORE regulator regulates to the âBootâ voltage,

it waits for the PGOOD logic HIGH signals from the Vccp

and Vcc_mch regulators. The Intersil ISL6227 is a perfect

choice for these two supplies, as it is a dual regulator and

has independent PGOOD functions for each supply. Once

these two supplies are within regulation, PGOODVccp and

PGOODVcc_mch will be high impedance, and will allow the

PGOOD of the ISL6217 to sink approximately 2.6mA to

ground through the internal MOSFET, shown in Figure 10.

The ISL6217 detects this current and starts an internal

PGOOD timer.

The current sourced into the PGOOD pin is critical for proper

start-up operation. The pullup resistor, Rpullup is sized to

give a minimum of 2.6mA of current sourced into the

PGOOD pin when the system is enabled and the Vccp and

Vcc_mch supplies are in regulation.

As given in the electrical specifications of this document, the

PGOOD MOSFET rDSON is given as 82Î© maximum. If 3.3V

is used as the supply, then the pullup resistor is given by the

following equation:

RPullup

Vsource

2.6mA

â rDSON(max) =

3.3 â 0.05(3.3)

2.6mA

â 82

â 1.2kÎ©

(EQ. 4)

where Vsource is the supply minus 5% for tolerance. This

will insure that approximately 2.6mA will be sourced into the

PGOOD pin for worst case conditions of low supply and

largest MOSFET rDSON.

Once the proper level of PGOOD current is detected, the

ISL6217 then captures the VID and regulates to this value.

The PGOOD timer is a function of the internal clock and

switching frequency. The internal PGOOD delay can be

calculated as follows:

Timer Delay = 3072 / FSW

(EQ. 5)

The ISL6217 controller regulates the CORE output voltage

to the VID command, and once the timer has expired, the

PGOOD output is allowed to go high.

are pulled low, which forces IMVP4_PWRGD low. PGOOD

of the ISL6217 is internally disabled during all VID and

Mode transitions.

Overvoltage

The VSEN voltage is compared with an internal

overvoltage protection (OVP) reference, set to 112% of the

VID voltage. If the VSEN voltage exceeds the OVP

reference, a comparator simultaneously sets the OV latch,

and pulls the PWM signal low. The drivers turn on the lower

MOSFETs, shunting the converter output to ground. Once

the output voltage falls below 102% of the set point, the

high side and low side MOSFETs are held off. This

prevents dumping of the output capacitors back through the

output inductors and lower MOSFETs, which would cause

a negative voltage on the CORE output.

This architecture eliminates the need of a high current,

Schottky diode on the output. If the overvoltage condition

persists, the outputs are cycled between output low and

output âoffâ, similar to a hysteretic regulator. The OV latch is

reset by cycling the VDD supply voltage to initiate a POR.

Depending on the mode of operation, the overvoltage

setpoint is 112% of the VID, Deep or Deeper Sleep

setpoint.

Undervoltage

The VSEN pin is also compared to an undervoltage (UV)

reference which is set to 84% of the VID, Deep or Deeper

Sleep set point, depending on the mode of operation. If the

VSEN voltage is below the UV reference for more than 32

consecutive phase clock cycles, the power good monitor

triggers the PGOOD pin to go low, and latches the chip off

until power is reset to the chip, or the EN pin is toggled.

Overcurrent

The RISEN resistor scales the voltage sampled across the

lower MOSFET and provides current feedback proportional

to the output current of each active channel (Refer to

Figure 9). The ISEN currents from all the active channels

are averaged together to form a scaled version of the total

output current, IAVERAGE. IAVERAGE is compared with

an internally generated overcurrent trip threshold, which is

proportional to the current sourced from the OCSET pin,

IOCSET. The overcurrent trip current source is

programmable and described in the âOvercurrent Setting -

OCSETâ section of this document.

If IAVERAGE exceeds the IOCSET level, an up/down

counter in enabled. If IAVERAGE does not fall below

IOCSET within 32 phase cycle counts, the PGOOD pin

transitions low and latches the chip off. If normal operation

resumes within the 32 phase cycle count window, the

controller will continue to operate normally (Refer to the

âBlock Diagramâ ).

NOTE: due to âDROOPâ there is inherent current limit, since load

current cannot exceed the amount that would command an

output voltage lower than 84% of the VID voltage. This

would result in an undervoltage shutdown, and would also

cause the PGOOD pin to transition low and latch the chip

off.

NOTE: the PGOOD functions of the VCC_CORE, Vccp and

Vcc_mch regulators are wire ORâd together to create the

system signal âIMVP4_PWRGDâ. If any of the supplies fall

outside the regulation window, their respective PGOOD pins

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